Datasheet ADS1015

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ADS1013 , ADS1014 , ADS1015
www.ti.com SBAS473E –MAY 2009–REVISED JANUARY 2018
Product Folder Links: ADS1013 ADS1014 ADS1015
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Feature Description (continued)
8.3.3 Full-Scale Range (FSR) and LSB Size
A programmable gain amplifier (PGA) is implemented before the ΔΣ ADC of the ADS1014 and ADS1015. The
full-scale range is configured by bits PGA[2:0] in the Config register and can be set to ±6.144 V, ±4.096 V,
±2.048 V, ±1.024 V, ±0.512 V, ±0.256 V. Table 1 shows the FSR together with the corresponding LSB size.
Equation 2 shows how to calculate the LSB size from the selected full-scale range.
LSB = FSR / 2
12
(2)
(1) This parameter expresses the full-scale range of the ADC scaling.
Do not apply more than VDD + 0.3 V to the analog inputs of the
device.
Table 1. Full-Scale Range and Corresponding LSB Size
FSR LSB SIZE
±6.144 V
(1)
3 mV
±4.096 V
(1)
2 mV
±2.048 V 1 mV
±1.024 V 0.5 mV
±0.512 V 0.25 mV
±0.256 V 0.125 mV
The FSR of the ADS1013 is fixed at ±2.048 V.
Analog input voltages must never exceed the analog input voltage limits given in the Absolute Maximum Ratings.
If a VDD supply voltage greater than 4 V is used, the ±6.144 V full-scale range allows input voltages to extend up
to the supply. Although in this case (or whenever the supply voltage is less than the full-scale range, a full-scale
ADC output code cannot be obtained. For example, with VDD = 3.3 V and FSR = ±4.096 V, only signals up to
V
IN
= ±3.3 V can be measured. The code range that represents voltages |V
IN
| > 3.3 V is not used in this case.
8.3.4 Voltage Reference
The ADS101x have an integrated voltage reference. An external reference cannot be used with these devices.
Errors associated with the initial voltage reference accuracy and the reference drift with temperature are included
in the gain error and gain drift specifications in the Electrical Characteristics table.
8.3.5 Oscillator
The ADS101x have an integrated oscillator running at 1 MHz. No external clock can be applied to operate these
devices. The internal oscillator drifts over temperature and time. The output data rate scales proportionally with
the oscillator frequency.
8.3.6 Output Data Rate and Conversion Time
The ADS101x offer programmable output data rates. Use the DR[2:0] bits in the Config register to select output
data rates of 128 SPS, 250 SPS, 490 SPS, 920 SPS, 1600 SPS, 2400 SPS, or 3300 SPS.
Conversions in the ADS101x settle within a single cycle; thus, the conversion time is equal to 1 / DR.
8.3.7 Digital Comparator (ADS1014 and ADS1015 Only)
The ADS1015 and ADS1014 feature a programmable digital comparator that can issue an alert on the
ALERT/RDY pin. The COMP_MODE bit in the Config register configures the comparator as either a traditional
comparator or a window comparator. In traditional comparator mode, the ALERT/RDY pin asserts (active low by
default) when conversion data exceeds the limit set in the high-threshold register (Hi_thresh). The comparator
then deasserts only when the conversion data falls below the limit set in the low-threshold register (Lo_thresh). In
window comparator mode, the ALERT/RDY pin asserts when the conversion data exceed the Hi_thresh register
or fall below the Lo_thresh register value.