Datasheet ADS1015
Table Of Contents
- 1 Features
- 2 Applications
- 3 Description
- Table of Contents
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Detailed Description
- 9 Application and Implementation
- 9.1 Application Information
- 9.2 Typical Application
- 9.2.1 Design Requirements
- 9.2.2 Detailed Design Procedure
- 9.2.2.1 Shunt Resistor Considerations
- 9.2.2.2 Operational Amplifier Considerations
- 9.2.2.3 ADC Input Common-Mode Considerations
- 9.2.2.4 Resistor (R1, R2, R3, R4) Considerations
- 9.2.2.5 Noise and Input Impedance Considerations
- 9.2.2.6 First-order RC Filter Considerations
- 9.2.2.7 Circuit Implementation
- 9.2.2.8 Results Summary
- 9.2.3 Application Curves
- 10 Power Supply Recommendations
- 11 Layout
- 12 Device and Documentation Support
- 13 Mechanical, Packaging, and Orderable Information
16
ADS1013
,
ADS1014
,
ADS1015
SBAS473E –MAY 2009–REVISED JANUARY 2018
www.ti.com
Product Folder Links: ADS1013 ADS1014 ADS1015
Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated
8.3.9 SMbus Alert Response
In latching comparator mode (COMP_LAT = 1), the ALERT/RDY pin asserts when the comparator detects a
conversion that exceeds the upper or lower threshold value. This assertion is latched and can be cleared only by
reading conversion data, or by issuing a successful SMBus alert response and reading the asserting device I
2
C
address. If conversion data exceed the upper or lower threshold values after being cleared, the pin reasserts.
This assertion does not affect conversions that are already in progress. The ALERT/RDY pin is an open-drain
output. This architecture allows several devices to share the same interface bus. When disabled, the pin holds a
high state so that the pin does not interfere with other devices on the same bus line.
When the master senses that the ALERT/RDY pin has latched, the master issues an SMBus alert command
(00011001) to the I
2
C bus. Any ADS1014 and ADS1015 data converters on the I
2
C bus with the ALERT/RDY
pins asserted respond to the command with the slave address. If more than one ADS101x on the I
2
C bus assert
the latched ALERT/RDY pin, arbitration during the address response portion of the SMBus alert determines
which device clears assertion. The device with the lowest I
2
C address always wins arbitration. If a device loses
arbitration, the device does not clear the comparator output pin assertion. The master then repeats the SMBus
alert response until all devices have the respective assertions cleared. In window comparator mode, the SMBus
alert status bit indicates a 1 if signals exceed the high threshold, and a 0 if signals exceed the low threshold.