Datasheet ADS1015

18
ADS1013 , ADS1014 , ADS1015
SBAS473E –MAY 2009–REVISED JANUARY 2018 www.ti.com
Product Folder Links: ADS1013 ADS1014 ADS1015
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8.5 Programming
8.5.1 I
2
C Interface
The ADS101x communicate through an I
2
C interface. I
2
C is a two-wire open-drain interface that supports multiple
devices and masters on a single bus. Devices on the I
2
C bus only drive the bus lines low by connecting them to
ground; the devices never drive the bus lines high. Instead, the bus wires are pulled high by pullup resistors, so
the bus wires are always high when no device is driving them low. As a result of this configuration, two devices
cannot conflict. If two devices drive the bus simultaneously, there is no driver contention.
Communication on the I
2
C bus always takes place between two devices, one acting as the master and the other
as the slave. Both the master and slave can read and write, but the slave can only do so under the direction of
the master. Some I
2
C devices can act as a master or slave, but the ADS101x can only act as a slave device.
An I
2
C bus consists of two lines: SDA and SCL. SDA carries data; SCL provides the clock. All data are
transmitted across the I
2
C bus in groups of eight bits. To send a bit on the I
2
C bus, drive the SDA line to the
appropriate level while SCL is low (a low on SDA indicates the bit is zero; a high indicates the bit is one). After
the SDA line settles, the SCL line is brought high, then low. This pulse on SCL clocks the SDA bit into the
receiver shift register. If the I
2
C bus is held idle for more than 25 ms, the bus times out.
The I
2
C bus is bidirectional; that is, the SDA line is used for both transmitting and receiving data. When the
master reads from a slave, the slave drives the data line; when the master sends to a slave, the master drives
the data line. The master always drives the clock line. The ADS101x cannot act as a master, and therefore can
never drive SCL.
Most of the time the bus is idle; no communication occurs, and both lines are high. When communication takes
place, the bus is active. Only a master device can start a communication and initiate a START condition on the
bus. Normally, the data line is only allowed to change state while the clock line is low. If the data line changes
state while the clock line is high, it is either a START condition or a STOP condition. A START condition occurs
when the clock line is high, and the data line goes from high to low. A STOP condition occurs when the clock line
is high, and the data line goes from low to high.
After the master issues a START condition, the master sends a byte that indicates with which slave device to
communicate. This byte is called the address byte. Each device on an I
2
C bus has a unique 7-bit address to
which it responds. The master sends an address in the address byte, together with a bit that indicates whether
the master wishes to read from or write to the slave device.
Every byte (address and data) transmitted on the I
2
C bus is acknowledged with an acknowledge bit. When the
master finishes sending a byte (eight data bits) to a slave, the master stops driving SDA and waits for the slave
to acknowledge the byte. The slave acknowledges the byte by pulling SDA low. The master then sends a clock
pulse to clock the acknowledge bit. Similarly, when the master completes reading a byte, the master pulls SDA
low to acknowledge this completion to the slave. The master then sends a clock pulse to clock the bit. The
master always drives the clock line.
If a device is not present on the bus, and the master attempts to address it, it receives a not-acknowledge
because no device is present at that address to pull the line low. A not-acknowledge is performed by simply
leaving SDA high during an acknowledge cycle.
When the master has finished communicating with a slave, it may issue a STOP condition. When a STOP
condition is issued, the bus becomes idle again. The master may also issue another START condition. When a
START condition is issued while the bus is active, it is called a repeated start condition.
The Timing Requirements section shows a timing diagram for the ADS101x I
2
C communication.