Datasheet ADS1015

19
ADS1013 , ADS1014 , ADS1015
www.ti.com SBAS473E –MAY 2009–REVISED JANUARY 2018
Product Folder Links: ADS1013 ADS1014 ADS1015
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Programming (continued)
8.5.1.1 I
2
C Address Selection
The ADS101x have one address pin, ADDR, that configures the I
2
C address of the device. This pin can be
connected to GND, VDD, SDA, or SCL, allowing for four different addresses to be selected with one pin, as
shown in Table 2. The state of address pin ADDR is sampled continuously. Use the GND, VDD and SCL
addresses first. If SDA is used as the device address, hold the SDA line low for at least 100 ns after the SCL line
goes low to make sure the device decodes the address correctly during I
2
C communication.
Table 2. ADDR Pin Connection and Corresponding Slave Address
ADDR PIN CONNECTION SLAVE ADDRESS
GND 1001000
VDD 1001001
SDA 1001010
SCL 1001011
8.5.1.2 I
2
C General Call
The ADS101x respond to the I
2
C general call address (0000000) if the eighth bit is 0. The devices acknowledge
the general call address and respond to commands in the second byte. If the second byte is 00000110 (06h), the
ADS101x reset the internal registers and enter a power-down state.
8.5.1.3 I
2
C Speed Modes
The I
2
C bus operates at one of three speeds. Standard mode allows a clock frequency of up to 100 kHz; fast
mode permits a clock frequency of up to 400 kHz; and high-speed mode (also called Hs mode) allows a clock
frequency of up to 3.4 MHz. The ADS101x are fully compatible with all three modes.
No special action is required to use the ADS101x in standard or fast mode, but high-speed mode must be
activated. To activate high-speed mode, send a special address byte of 00001xxx following the START condition,
where xxx are bits unique to the Hs-capable master. This byte is called the Hs master code, and is different from
normal address bytes; the eighth bit does not indicate read/write status. The ADS101x do not acknowledge this
byte; the I
2
C specification prohibits acknowledgment of the Hs master code. Upon receiving a master code, the
ADS101x switch on Hs mode filters, and communicate at up to 3.4 MHz. The ADS101x switch out of Hs mode
with the next STOP condition.
For more information on high-speed mode, consult the I
2
C specification.
8.5.2 Slave Mode Operations
The ADS101x act as slave receivers or slave transmitters. The ADS101x cannot drive the SCL line as slave
devices.
8.5.2.1 Receive Mode
In slave receive mode, the first byte transmitted from the master to the slave consists of the 7-bit device address
followed by a low R/W bit. The next byte transmitted by the master is the Address Pointer register. The ADS101x
then acknowledge receipt of the Address Pointer register byte. The next two bytes are written to the address
given by the register address pointer bits, P[1:0]. The ADS101x acknowledge each byte sent. Register bytes are
sent with the most significant byte first, followed by the least significant byte.
8.5.2.2 Transmit Mode
In slave transmit mode, the first byte transmitted by the master is the 7-bit slave address followed by the high
R/W bit. This byte places the slave into transmit mode and indicates that the ADS101x are being read from. The
next byte transmitted by the slave is the most significant byte of the register that is indicated by the register
address pointer bits, P[1:0]. This byte is followed by an acknowledgment from the master. The remaining least
significant byte is then sent by the slave and is followed by an acknowledgment from the master. The master
may terminate transmission after any byte by not acknowledging or issuing a START or STOP condition.