Datasheet ADS1015
Table Of Contents
- 1 Features
- 2 Applications
- 3 Description
- Table of Contents
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Detailed Description
- 9 Application and Implementation
- 9.1 Application Information
- 9.2 Typical Application
- 9.2.1 Design Requirements
- 9.2.2 Detailed Design Procedure
- 9.2.2.1 Shunt Resistor Considerations
- 9.2.2.2 Operational Amplifier Considerations
- 9.2.2.3 ADC Input Common-Mode Considerations
- 9.2.2.4 Resistor (R1, R2, R3, R4) Considerations
- 9.2.2.5 Noise and Input Impedance Considerations
- 9.2.2.6 First-order RC Filter Considerations
- 9.2.2.7 Circuit Implementation
- 9.2.2.8 Results Summary
- 9.2.3 Application Curves
- 10 Power Supply Recommendations
- 11 Layout
- 12 Device and Documentation Support
- 13 Mechanical, Packaging, and Orderable Information
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ADS1013
,
ADS1014
,
ADS1015
SBAS473E –MAY 2009–REVISED JANUARY 2018
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Product Folder Links: ADS1013 ADS1014 ADS1015
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8.6.4 Lo_thresh (P[1:0] = 2h) [reset = 8000h] and Hi_thresh (P[1:0] = 3h) [reset = 7FFFh] Registers
The upper and lower threshold values used by the comparator are stored in two 16-bit registers in two's
complement format. The comparator is implemented as a digital comparator; therefore, the values in these
registers must be updated whenever the PGA settings are changed.
The conversion-ready function of the ALERT/RDY pin is enabled by setting the Hi_thresh register MSB to 1 and
the Lo_thresh register MSB to 0. To use the comparator function of the ALERT/RDY pin, the Hi_thresh register
value must always be greater than the Lo_thresh register value. The threshold register formats are shown in
Figure 22. When set to RDY mode, the ALERT/RDY pin outputs the OS bit when in single-shot mode, and
provides a continuous-conversion ready pulse when in continuous-conversion mode.
Figure 22. Lo_thresh Register
15 14 13 12 11 10 9 8
Lo_thresh11 Lo_thresh10 Lo_thresh9 Lo_thresh8 Lo_thresh7 Lo_thresh6 Lo_thresh5 Lo_thresh4
R/W-1h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
Lo_thresh3 Lo_thresh2 Lo_thresh1 Lo_thresh0 0 0 0 0
R/W-0h R/W-0h R/W-0h R/W-0h R-0h R-0h R-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 23. Hi_thresh Register
15 14 13 12 11 10 9 8
Hi_thresh11 Hi_thresh10 Hi_thresh9 Hi_thresh8 Hi_thresh7 Hi_thresh6 Hi_thresh5 Hi_thresh4
R/W-0h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h
7 6 5 4 3 2 1 0
Hi_thresh3 Hi_thresh2 Hi_thresh1 Hi_thresh0 1 1 1 1
R/W-1h R/W-1h R/W-1h R/W-1h R-1h R-1h R-1h R-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7. Lo_thresh and Hi_thresh Register Field Descriptions
Bit Field Type Reset Description
15:4 Lo_thresh[11:0] R/W 800h Low threshold value
15:4 Hi_thresh[11:0] R/W 7FFh High threshold value