Datasheet ADS1015
Table Of Contents
- 1 Features
- 2 Applications
- 3 Description
- Table of Contents
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Detailed Description
- 9 Application and Implementation
- 9.1 Application Information
- 9.2 Typical Application
- 9.2.1 Design Requirements
- 9.2.2 Detailed Design Procedure
- 9.2.2.1 Shunt Resistor Considerations
- 9.2.2.2 Operational Amplifier Considerations
- 9.2.2.3 ADC Input Common-Mode Considerations
- 9.2.2.4 Resistor (R1, R2, R3, R4) Considerations
- 9.2.2.5 Noise and Input Impedance Considerations
- 9.2.2.6 First-order RC Filter Considerations
- 9.2.2.7 Circuit Implementation
- 9.2.2.8 Results Summary
- 9.2.3 Application Curves
- 10 Power Supply Recommendations
- 11 Layout
- 12 Device and Documentation Support
- 13 Mechanical, Packaging, and Orderable Information
2
AIN0
VDD
AIN3
AIN2
SCL
VDD
Device
GND
AIN1
SCL
Vias connect to either bottom layer or
an internal plane. The bottom layer or
internal plane are dedicated GND planes
ADDR
ALERT/RDY
ADDR
SDA
SDA
4 7
65
10
8
9
3
1
ALERT/RDY
AIN2
AIN3
AIN0
AIN1
SCL
SDA
AIN0
AIN1
SCL
SDA
VDD
AIN3
AIN2
1
GND
Device
AIN2
VDD
10
9
4
5
6
7
8
Vias connect to either bottom layer or
an internal plane. The bottom layer or
internal plane are dedicated GND planes
ADDR
ALERT/RDY
3
1
2
ALERT/RDY
ADDR
AIN3
AIN0
AIN1
38
ADS1013
,
ADS1014
,
ADS1015
SBAS473E –MAY 2009–REVISED JANUARY 2018
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Product Folder Links: ADS1013 ADS1014 ADS1015
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11.2 Layout Example
Figure 34. ADS1015 X2QFN Package
Figure 35. ADS1015 VSSOP Package