Datasheet ADS1015
Table Of Contents
- 1 Features
- 2 Applications
- 3 Description
- Table of Contents
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Detailed Description
- 9 Application and Implementation
- 9.1 Application Information
- 9.2 Typical Application
- 9.2.1 Design Requirements
- 9.2.2 Detailed Design Procedure
- 9.2.2.1 Shunt Resistor Considerations
- 9.2.2.2 Operational Amplifier Considerations
- 9.2.2.3 ADC Input Common-Mode Considerations
- 9.2.2.4 Resistor (R1, R2, R3, R4) Considerations
- 9.2.2.5 Noise and Input Impedance Considerations
- 9.2.2.6 First-order RC Filter Considerations
- 9.2.2.7 Circuit Implementation
- 9.2.2.8 Results Summary
- 9.2.3 Application Curves
- 10 Power Supply Recommendations
- 11 Layout
- 12 Device and Documentation Support
- 13 Mechanical, Packaging, and Orderable Information
7
ADS1013
,
ADS1014
,
ADS1015
www.ti.com
SBAS473E –MAY 2009–REVISED JANUARY 2018
Product Folder Links: ADS1013 ADS1014 ADS1015
Submit Documentation FeedbackCopyright © 2009–2018, Texas Instruments Incorporated
(1) This parameter expresses the full-scale range of the ADC scaling. No more than VDD + 0.3 V must be applied to the analog inputs of
the device. See Table 1 more information.
(2) Best-fit INL; covers 99% of full-scale.
(3) Includes all errors from onboard PGA and voltage reference.
7.5 Electrical Characteristics
At VDD = 3.3 V, data rate = 128 SPS, and full-scale input-voltage range (FSR) = ±2.048 V (unless otherwise noted).
Maximum and minimum specifications apply from T
A
= –40°C to +125°C. Typical specifications are at T
A
= 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
Common-mode input impedance
FSR = ±6.144 V
(1)
10
MΩ
FSR = ±4.096 V
(1)
, FSR = ±2.048 V 6
FSR = ±1.024 V 3
FSR = ±0.512 V, FSR = ±0.256 V 100
Differential input impedance
FSR = ±6.144 V
(1)
22
MΩ
FSR = ±4.096 V
(1)
15
FSR = ±2.048 V 4.9
FSR = ±1.024 V 2.4
FSR = ±0.512 V, ±0.256 V 710 kΩ
SYSTEM PERFORMANCE
Resolution (no missing codes) 12 Bits
DR Data rate 128, 250, 490, 920, 1600, 2400, 3300 SPS
Data rate variation All data rates –10% 10%
INL Integral nonlinearity DR = 128 SPS, FSR = ±2.048 V
(2)
0.5 LSB
Offset error
FSR = ±2.048 V, differential inputs -0.5 0 0.5
LSB
FSR = ±2.048 V, single-ended inputs ±0.25
Offset drift over temperature FSR = ±2.048 V 0.005 LSB/°C
Long-term offset drift
FSR = ±2.048 V, T
A
= 125°C, 1000
hrs
±1 LSB
Offset channel match Match between any two inputs 0.25 LSB
Gain error
(3)
FSR = ±2.048 V, T
A
= 25°C 0.05% 0.25%
Gain drift over temperature
(3)
FSR = ±0.256 V 7
ppm/°CFSR = ±2.048 V 5 40
FSR = ±6.144 V
(1)
5
Long-term gain drift
FSR = ±2.048 V, T
A
= 125°C, 1000
hrs
±0.05 %
Gain match
(3)
Match between any two gains 0.02% 0.1%
Gain channel match Match between any two inputs 0.05% 0.1%
DIGITAL INPUT/OUTPUT
V
IH
High-level input voltage 0.7 VDD VDD V
V
IL
Low-level input voltage GND 0.3 VDD V
V
OL
Low-level output voltage I
OL
= 3 mA GND 0.15 0.4 V
Input leakage current GND < V
DIG
< VDD –10 10 µA
POWER-SUPPLY
I
VDD
Supply current
Power-down
T
A
= 25°C 0.5 2
µA
5
Operating
T
A
= 25°C 150 200
300
P
D
Power dissipation
VDD = 5.0 V 0.9
mWVDD = 3.3 V 0.5
VDD = 2.0 V 0.3