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UM10360

LPC17xx User manual

Rev. 2 — 19 August 2010 User manual

Document information

Info Content

Keywords LPC1769, LPC1768, LPC1767, LPC1766, LPC1765, LPC1764, LPC1763,

LPC1759, LPC1758, LPC1756, LPC1754, LPC1752, LPC1751, ARM, ARM

Cortex-M3, 32-bit, USB, Ethernet, CAN, I2S, Microcontroller

Abstract LPC17xx user manual

Summary of content (840 pages)

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UM10360 LPC17xx User manual Rev.
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UM10360 NXP Semiconductors LPC17xx user manual Revision history Rev Date Description 2 20100819 LPC17xx user manual revision. Modifications: 1 20100104 • • • • UART0/1/2/3: FIFOLVL register removed. • • • Clocking and power control: add bit 15 (PCGPIO) to PCONP register (Table 46). • • • Motor control PWM: update description of match and limit registers. ADC: reset value of the ADCTRM register changed to 0xF00 (Table 536). Timer0/1/2/3: Description of DMA operation updated.
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UM10360 Chapter 1: LPC17xx Introductory information Rev. 2 — 19 August 2010 User manual 1.1 Introduction The LPC17xx is an ARM Cortex-M3 based microcontroller for embedded applications requiring a high level of integration and low power dissipation. The ARM Cortex-M3 is a next generation core that offers system enhancements such as modernized debug features and a higher level of support block integration. High speed versions (LPC1769 and LPC1759) operate at up to a 120 MHz CPU frequency.
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UM10360 NXP Semiconductors Chapter 1: LPC17xx Introductory information 1.2 Features Refer to Section 1.4.1 for details of features on specific part numbers. • ARM Cortex-M3 processor, running at frequencies of up to 120 MHz on high speed versions (LPC1769 and LPC1759), up to 100 MHz on other versions. A Memory Protection Unit (MPU) supporting eight regions is included. • ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
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UM10360 NXP Semiconductors Chapter 1: LPC17xx Introductory information – I2S (Inter-IC Sound) interface for digital audio input or output, with fractional rate control. The I2S interface can be used with the GPDMA. The I2S interface supports 3-wire data transmit and receive or 4-wire combined transmit and receive connections, as well as master clock output.
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UM10360 NXP Semiconductors Chapter 1: LPC17xx Introductory information • Processor wake-up from Power-down mode via any interrupt able to operate during Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet wake-up interrupt, CAN bus activity, PORT0/2 pin interrupt, and NMI). • • • • • Each peripheral has its own clock divider for further power savings. Brownout detect with separate threshold for interrupt and forced reset. On-chip Power-On Reset (POR).
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UM10360 NXP Semiconductors Chapter 1: LPC17xx Introductory information 1.4 Ordering information Table 1. Ordering information Type number Package Name Description Version LQFP100 plastic low profile quad flat package; 100 leads; body 14 × 14 × 1.4 mm SOT407-1 LPC1769FBD100 LPC1768FBD100 LPC1767FBD100 LPC1766FBD100 LPC1765FBD100 LPC1764FBD100 LPC1763FBD100 LPC1768FET100 TFBGA100 plastic thin fine-pitch ball grid array package; 100 balls; body 9 x 9 x 0.
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UM10360 NXP Semiconductors Chapter 1: LPC17xx Introductory information ARM Cortex-M3 DMA controller Ethernet 10/100 MAC USB device, host, OTG Clocks and Controls System bus D-code bus I-code bus Clock Generation, Power Control, Brownout Detect, and other system functions Flash Accelerator Flash 512 kB SRAM 64 kB Multilayer AHB Matrix High Speed GPIO RST Test/Debug Interface USB interface Xtalout JTAG interface Trace Module Ethernet PHY interface Trace Port Xtalin 1.
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UM10360 NXP Semiconductors Chapter 1: LPC17xx Introductory information 1.6 Architectural overview The ARM Cortex-M3 includes three AHB-Lite buses, one system bus and the I-code and D-code buses which are faster and are used similarly to TCM interfaces: one bus dedicated for instruction fetch (I-code) and one bus for data access (D-code). The use of two core buses allows for simultaneous operations if concurrent operations target different devices.
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UM10360 NXP Semiconductors Chapter 1: LPC17xx Introductory information Debug related options: • A JTAG debug interface is included. • Serial Wire Debug is included. Serial Wire Debug allows debug operations using only 2 wires, simple trace functions can be added with a third wire. • The Embedded Trace Macrocell (ETM) is included. The ETM provides instruction trace capabilities. • The Data Watchpoint and Trace (DWT) unit is included.
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UM10360 NXP Semiconductors Chapter 1: LPC17xx Introductory information ARM Cortex-M3 D-code bus EMULATION TRACE MODULE TEST/DEBUG INTERFACE I-code bus DMA controller Ethernet 10/100 MAC RST clock generation, CLK power control, OUT and other system functions Vdd voltage regulator clocks and controls USB device, host, OTG Xtalout USB interface X32Kin Ethernet PHY interface Debug Port X32Kout JTAG interface Xtalin 1.
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UM10360 Chapter 2: LPC17xx Memory map Rev. 2 — 19 August 2010 User manual 2.1 Memory map and peripheral addressing The ARM Cortex-M3 processor has a single 4 GB address space. The following table shows how this space is used on the LPC17xx. Table 3. LPC17xx memory usage and details Address range General Use Address range details and description 0x0000 0000 to 0x1FFF FFFF On-chip non-volatile memory 0x0000 0000 - 0x0007 FFFF For devices with 512 kB of flash memory.
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 31 0x400B 4000 0x400B 0000 15 14 13 0x400A 8000 10 I2S 0x400A 4000 9 reserved 0x400A 0000 8 I2C2
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UM10360 NXP Semiconductors Chapter 2: LPC17xx Memory map Figure 3 and Table 4 show different views of the peripheral address space. The AHB peripheral area is 2 megabyte in size, and is divided to allow for up to 128 peripherals. The APB peripheral area is 1 megabyte in size and is divided to allow for up to 64 peripherals. Each peripheral of either type is allocated 16 kilobytes of space. This allows simplifying the address decoding for each peripheral.
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UM10360 NXP Semiconductors Chapter 2: LPC17xx Memory map Table 5.
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UM10360 NXP Semiconductors Chapter 2: LPC17xx Memory map For these areas, both attempted data access and instruction fetch generate an exception. In addition, a Bus Fault exception is generated for any instruction fetch that maps to an AHB or APB peripheral address. Within the address space of an existing APB peripheral, an exception is not generated in response to an access to an undefined address.
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UM10360 Chapter 3: LPC17xx System control Rev. 2 — 19 August 2010 User manual 3.1 Introduction The system control block includes several system features and control registers for a number of functions that are not related to specific peripheral devices.
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UM10360 NXP Semiconductors Chapter 3: LPC17xx System control 3.3 Register description All registers, regardless of size, are on word address boundaries. Details of the registers appear in the description of each function. Table 7.
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UM10360 NXP Semiconductors Chapter 3: LPC17xx System control external reset Reset to the on-chip circuitry C Q watchdog reset Reset to PCON.PD S POR BOD WAKE-UP TIMER START power-down COUNT 2 n EINT0 wake-up EINT1 wake-up Q internal RC oscillator S write “1” from APB EINT2 wake-up EINT3 wake-up RTC wake-up BOD wake-up Ethernet MAC wake-up reset APB read of PDBIT in PCON USB need_clk wake-up CAN wake-up GPIO0 port wake-up GPIO2 port wake-up Fig 4.
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UM10360 NXP Semiconductors Chapter 3: LPC17xx System control IRC starts IRC stable IRC status RESET VDD(REG)(3V3) valid threshold GND 60 μs 1 μs; IRC stability count boot time supply ramp-up time 7 μs 181 μs 224 μs user code processor status flash read starts Fig 5. flash read finishes boot code execution finishes; user code starts Example of start-up after reset UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev.
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UM10360 NXP Semiconductors Chapter 3: LPC17xx System control 3.4.1 Reset Source Identification Register (RSID - 0x400F C180) This register contains one bit for each source of Reset. Writing a 1 to any of these bits clears the corresponding read-side bit to 0. The interactions among the four sources are described below. Table 8.
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UM10360 NXP Semiconductors Chapter 3: LPC17xx System control 3.5 Brown-out detection The LPC17xx includes a Brown-Out Detector (BOD) that provides 2-stage monitoring of the voltage on the VDD(REG)(3V3) pins. If this voltage falls below the BOD interrupt trip level (typically 2.2 V under nominal room temperature conditions), the BOD asserts an interrupt signal to the NVIC.
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UM10360 NXP Semiconductors Chapter 3: LPC17xx System control 3.6 External interrupt inputs TheLPC17xx includes four External Interrupt Inputs as selectable pin functions. The logic of an individual external interrupt is represented in Figure 6. In addition, external interrupts have the ability to wake up the CPU from Power-down mode. Refer to Section 4.8.8 “Wake-up from Reduced Power Modes” for details.
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UM10360 NXP Semiconductors Chapter 3: LPC17xx System control 3.6.1 Register description The external interrupt function has four registers associated with it. The EXTINT register contains the interrupt flags. The EXTMODE and EXTPOLAR registers specify the level and edge sensitivity parameters. Table 9. External Interrupt registers Name Description Access Reset Address value[1] EXTINT The External Interrupt Flag Register contains interrupt flags for EINT0, EINT1, EINT2 and EINT3. See Table 10.
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UM10360 NXP Semiconductors Chapter 3: LPC17xx System control Table 10. External Interrupt Flag register (EXTINT - address 0x400F C140) bit description Bit Symbol Description Reset value 0 EINT0 0 In level-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the selected edge occurs on the pin.
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UM10360 NXP Semiconductors Chapter 3: LPC17xx System control Table 11. External Interrupt Mode register (EXTMODE - address 0x400F C148) bit description Bit Symbol Value Description Reset value 0 EXTMODE0 0 Level-sensitivity is selected for EINT0. 0 1 EINT0 is edge sensitive. 1 2 3 EXTMODE1 EXTMODE2 EXTMODE3 31:4 - 0 Level-sensitivity is selected for EINT1. 1 EINT1 is edge sensitive. 0 Level-sensitivity is selected for EINT2. 1 EINT2 is edge sensitive.
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UM10360 NXP Semiconductors Chapter 3: LPC17xx System control Table 12. Bit Symbol 3 EXTPOLAR3 0 EINT3 is low-active or falling-edge sensitive (depending on EXTMODE3). 1 EINT3 is high-active or rising-edge sensitive (depending on EXTMODE3). - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
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UM10360 NXP Semiconductors Chapter 3: LPC17xx System control 3.7 Other system controls and status flags Some aspects of controlling LPC17xx operation that do not fit into peripheral or other registers are grouped here. 3.7.1 System Controls and Status register (SCS - 0x400F C1A0) The SCS register contains several control/status bits related to the main oscillator.
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UM10360 Chapter 4: LPC17xx Clocking and power control Rev. 2 — 19 August 2010 User manual 4.1 Summary of clocking and power control functions This section describes the generation of the various clocks needed by the LPC17xx and options of clock source selection, as well as power control and wake-up from reduced power modes.
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UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control 4.2 Register description All registers, regardless of size, are on word address boundaries. Details of the registers appear in the description of each function. Table 14.
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UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control 4.3 Oscillators The LPC17xx includes three independent oscillators. These are the Main Oscillator, the Internal RC Oscillator, and the RTC oscillator. Each oscillator can be used for more than one purpose as required in a particular application. This can be seen in Figure 7. Following Reset, the LPC17xx will operate from the Internal RC Oscillator until switched by software.
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UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control LPC17xx XTAL1 LPC17xx XTAL2 XTAL1 XTAL2 L <=> CC CL CP Xtal Clock CX1 CX2 a) Fig 8. RS b) c) Oscillator modes and models: a) slave mode of operation, b) oscillation mode of operation, c) external crystal model used for CX1/X2 evaluation Table 15.
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UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control point, software can control switching to the main oscillator as a clock source. Prior to starting the main oscillator, a frequency range must be selected by configuring the OSCRANGE bit in the SCS register. 4.3.3 RTC oscillator The RTC oscillator provides a 1 Hz clock to the RTC and a 32 kHz clock output that can be used as the clock source for PLL0 and CPU and/or the watchdog timer.
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UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control 4.4 Clock source selection multiplexer Several clock sources may be chosen to drive PLL0 and ultimately the CPU and on-chip peripheral devices. The clock sources available are the main oscillator, the RTC oscillator, and the Internal RC oscillator. The clock source selection can only be changed safely when PLL0 is not connected. For a detailed description of how to change the clock source in a system using PLL0 see Section 4.5.
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UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control 4.5 PLL0 (Phase Locked Loop 0) PLL0 accepts an input clock frequency in the range of 32 kHz to 50 MHz. The clock source is selected in the CLKSRCSEL register (see Section 4.4). The input frequency is multiplied up to a high frequency, then divided down to provide the actual clock used by the CPU, peripherals, and optionally the USB subsystem. Note that the USB subsystem has its own dedicated PLL (see Section 4.6).
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UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control 4.5.2 PLL0 register description PLL0 is controlled by the registers shown in Table 18. More detailed descriptions follow. Warning: Improper setting of PLL0 values may result in incorrect operation of the device! Table 18. PLL0 registers Name Description PLL0CON PLL0 Control Register. Holding register for R/W updating PLL0 control bits.
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UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control output clock. Changes to the PLL0CON register do not take effect until a correct PLL0 feed sequence has been given (see Section 4.5.8 “PLL0 Feed register (PLL0FEED 0x400F C08C)”). Table 19. PLL Control register (PLL0CON - address 0x400F C080) bit description Bit Symbol Description Reset value 0 PLLE0 PLL0 Enable.
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UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control Table 21. UM10360 User manual Multiplier values for PLL0 with a 32 kHz input Multiplier (M) Pre-divide (N) FCCO Multiplier (M) Pre-divide (N) FCCO 4272 1 279.9698 12085 2 396.0013 4395 1 288.0307 12207 2 399.9990 4578 1 300.0238 12817 2 419.9875 4725 1 309.6576 12817 3 279.9916 4807 1 315.0316 13184 2 432.0133 5127 1 336.0031 13184 3 288.0089 5188 1 340.0008 13672 2 448.
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UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control 4.5.5 PLL0 Status register (PLL0STAT - 0x400F C088) The read-only PLL0STAT register provides the actual PLL0 parameters that are in effect at the time it is read, as well as PLL0 status. PLL0STAT may disagree with values found in PLL0CON and PLL0CFG because changes to those registers do not take effect until a proper PLL0 feed has occurred (see Section 4.5.8 “PLL0 Feed register (PLL0FEED 0x400F C08C)”). Table 22.
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UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control 4.5.7 PLL0 Modes The combinations of PLLE0 and PLLC0 are shown in Table 23. Table 23. PLL control bit combinations PLLC0 PLLE0 PLL Function 0 0 PLL0 is turned off and disconnected. PLL0 outputs the unmodified clock input. 0 1 PLL0 is active, but not yet connected. PLL0 can be connected after PLOCK0 is asserted. 1 0 Same as 00 combination. This prevents the possibility of PLL0 being connected without also being enabled.
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UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control Table 25. PLL frequency parameter Parameter Description FIN the frequency of PLLCLKIN from the Clock Source Selection Multiplexer. FCCO the frequency of the PLLCLK (output of the PLL Current Controlled Oscillator) N PLL0 Pre-divider value from the NSEL0 bits in the PLL0CFG register (PLL0CFG NSEL0 field + 1). N is an integer from 1 through 32.
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UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control Table 26.
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UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control 4.5.12 Examples of PLL0 settings The following table gives a summary of examples that illustrate selecting PLL0 values based on different system requirements. Table 27. Summary of PLL0 examples Example 1 Description • The PLL0 clock source is 10 MHz. • PLL0 is not used as the USB clock source, or the USB interface is not used. • The desired CPU clock is 100 MHz. 2 • The PLL0 clock source is 4 MHz.
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UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control Example 2 Assumptions: • The USB interface will be used in the application and will be clocked from PLL0. • The desired CPU rate is 60 MHz. • An external 4 MHz crystal or clock source will be used as the system clock source. This clock source could be the Internal RC oscillator (IRC).
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UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control Example 3 Assumptions: • The USB interface will not be used in the application, or will be clocked by PLL1. • The desired CPU rate is 72 MHz • The 32.768 kHz RTC clock source will be used as the system clock source Calculations: M = (FCCO × N) / (2 × FIN) The smallest integer multiple of the desired CPU clock rate that is within the PLL0 operating range is 288 MHz (4 × 72 MHz).
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UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control 4.5.13 PLL0 setup sequence The following sequence must be followed step by step in order to have PLL0 initialized and running: 1. Disconnect PLL0 with one feed sequence if PLL0 is already connected. 2. Disable PLL0 with one feed sequence. 3. Change the CPU Clock Divider setting to speed up operation without PLL0, if desired. 4. Write to the Clock Source Selection Control register to change the clock source if needed. 5.
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UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control 4.6 PLL1 (Phase Locked Loop 1) PLL1 receives its clock input from the main oscillator only and can be used to provide a fixed 48 MHz clock only to the USB subsystem. This is an option in addition to the possibility of generating the USB clock from PLL0. PLL1 is disabled and powered off on reset. If PLL1 is left disabled, the USB clock can be supplied by PLL0 if everything is set up to provide 48 MHz through that route.
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UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control Table 29. PLL1 registers Name Description Access Reset Address value[1] PLL1CFG PLL1 Configuration Register. Holding register for updating PLL1 configuration values. Values written to this register do not take effect until a valid PLL1 feed sequence has taken place. R/W PLL1STAT PLL1FEED [1] 0 0x400F C0A4 PLL1 Status Register. Read-back register for RO PLL1 control and configuration information.
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UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control Table 30. PLL1 Control register (PLL1CON - address 0x400F C0A0) bit description Bit Symbol Description Reset value 0 PLLE1 PLL1 Enable. When one, and after a valid PLL1 feed, this bit will activate PLL1 and allow it to lock to the requested frequency. See PLL1STAT register, Table 32. 0 1 PLLC1 PLL1 Connect.
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UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control Table 32. PLL1 Status register (PLL1STAT - address 0x400F C0A8) bit description Bit Symbol Description 4:0 MSEL1 Read-back for the PLL1 Multiplier value. This is the value currently 0 used by PLL1. 6:5 PSEL1 Read-back for the PLL1 Divider value. This is the value currently used by PLL1. 0 7 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
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UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control 4.6.6 PLL1 Feed register (PLL1FEED - 0x400F C0AC) A correct feed sequence must be written to the PLL1FEED register in order for changes to the PLL1CON and PLL1CFG registers to take effect. The feed sequence is: 1. Write the value 0xAA to PLL1FEED. 2. Write the value 0x55 to PLL1FEED.
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UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control 4.6.8 PLL1 frequency calculation The PLL1 equations use the following parameters: Table 35.
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UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control Table 36. PLL1 Divider values Values allowed for using PLL1 with USB are highlighted. PSEL1 Bits (PLL1CFG bits [6:5]) Value of P 00 1 01 2 10 4 11 8 Table 37. PLL1 Multiplier values Values allowed for using PLL1 with USB are highlighted. UM10360 User manual MSEL1 Bits (PLL1CFG bits [4:0]) Value of M 00000 1 00001 2 00010 3 00011 4 ... ...
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UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control 4.7 Clock dividers The output of the PLL0 must be divided down for use by the CPU and the USB subsystem (if used with PLL0, see Section 4.6). Separate dividers are provided such that the CPU frequency can be determined independently from the USB subsystem, which always requires 48 MHz with a 50% duty cycle for proper operation. USB PLL settings (PLL1...) osc_clk USB PLL select (PLL1CON) USB PLL (PLL1) main PLL settings (PLL0...
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UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control Table 38. CPU Clock Configuration register (CCLKCFG - address 0x400F C104) bit description Bit Symbol 7:0 CCLKSEL 31:8 - Value Description Reset value Selects the divide value for creating the CPU clock (CCLK) from the PLL0 output. 0x00 0 pllclk is divided by 1 to produce the CPU clock. This setting is not allowed when the PLL0 is connected, because the rate would always be greater than the maximum allowed CPU clock.
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UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control Table 39. USB Clock Configuration register (USBCLKCFG - address 0x400F C108) bit description Bit Symbol 3:0 USBSEL Value Description Reset value Selects the divide value for creating the USB clock from the PLL0 output. Only the values shown below can produce even number multiples of 48 MHz from the PLL0 output. 0 Warning: Improper setting of this value will result in incorrect operation of the USB interface.
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UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control Table 41. Bit Symbol Description Reset value 1:0 PCLK_QEI Peripheral clock selection for the Quadrature Encoder Interface. 00 3:2 PCLK_GPIOINT Peripheral clock selection for GPIO interrupts. 00 5:4 PCLK_PCB Peripheral clock selection for the Pin Connect block. 00 7:6 PCLK_I2C1 Peripheral clock selection for I2C1. 00 9:8 - Reserved. NA 11:10 PCLK_SSP0 Peripheral clock selection for SSP0.
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UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control 4.8 Power control The LPC17xx supports a variety of power control features: Sleep mode, Deep Sleep mode, Power-down mode, and Deep Power-down mode. The CPU clock rate may also be controlled as needed by changing clock sources, re-configuring PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements.
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UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control When the chip enters the Deep Sleep mode, the main oscillator is powered down, nearly all clocks are stopped, and the DSFLAG bit in PCON is set, see Table 44. The IRC remains running and can be configured to drive the Watchdog Timer, allowing the Watchdog to wake up the CPU. The 32 kHz RTC oscillator is not stopped and RTC interrupts may be used as a wake-up source. The flash is left in the standby mode allowing a quick wake-up.
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UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control 4.8.4 Deep Power-down mode In Deep Power-down mode, power is shut off to the entire chip with the exception of the Real-Time Clock, the RESET pin, the WIC, and the RTC backup registers. Entry to Deep Power-down mode causes the DPDFLAG bit in PCON to be set, see Table 44. To optimize power conservation, the user has the additional option of turning off or retaining power to the 32 kHz oscillator.
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UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control 4.8.7 Power Mode Control register (PCON - 0x400F C0C0) Controls for some reduced power modes and other power related controls are contained in the PCON register, as described in Table 44. Table 44. Power Mode Control register (PCON - address 0x400F C0C0) bit description Bit Symbol Description Reset value 0 PM0 Power mode control bit 0. This bit controls entry to the Power-down mode. See Section 4.8.7.1 below for details.
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UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control 4.8.7.1 Encoding of Reduced Power Modes The PM1and PM0 bits in PCON allow entering reduced power modes as needed. The encoding of these bits allows backward compatibility with devices that previously only supported Sleep and Power-down modes. Table 45 below shows the encoding for the three reduced power modes supported by the LPC17xx. Table 45.
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UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control Some peripherals, particularly those that include analog functions, may consume power that is not clock dependent. These peripherals may contain a separate disable control that turns off additional circuitry to reduce power. Information on peripheral specific power saving features may be found in the chapter describing that peripheral. Each bit in PCONP controls one peripheral as shown in Table 46.
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UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control Table 46. Power Control for Peripherals register (PCONP - address 0x400F C0C4) bit description Bit Symbol Description Reset value 27 PCI2S I2S interface power/clock control bit. 0 28 - Reserved. NA 29 PCGPDMA GPDMA function power/clock control bit. 0 30 PCENET Ethernet block power/clock control bit. 0 31 PCUSB USB interface power/clock control bit.
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UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control 4.9 Wake-up timer The LPC17xx begins operation at power-up and when awakened from Power-down mode by using the 4 MHz IRC oscillator as the clock source. This allows chip operation to begin quickly. If the main oscillator or one or both PLLs are needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source.
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UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control 4.10 External clock output pin For system test and development purposes, any one of several internal clocks may be brought out on the CLKOUT function available on the P1.27 pin, as shown in Figure 12. Clocks that may be observed via CLKOUT are the CPU clock (cclk), the main oscillator (osc_clk), the internal RC oscillator (irc_osc), the USB clock (usb_clk), and the RTC clock (rtc_clk).
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UM10360 NXP Semiconductors Chapter 4: LPC17xx Clocking and power control Table 47. Clock Output Configuration register (CLKOUTCFG - 0x400F C1C8) bit description Bit Symbol Value Description 7:4 CLKOUTDIV Integer value to divide the output clock by, minus one. 0000 Clock is divided by 1. 0001 Clock is divided by 2. 0010 Clock is divided by 3. ... ... 1111 User manual 0 Clock is divided by 16. 8 CLKOUT_EN CLKOUT enable control, allows switching the CLKOUT source without glitches.
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UM10360 Chapter 5: LPC17xx Flash accelerator Rev. 2 — 19 August 2010 User manual 5.1 Introduction The flash accelerator block in the LPC17xx allows maximization of the performance of the Cortex-M3 processor when it is running code from flash memory, while also saving power. The flash accelerator also provides speed and power improvements for data accesses to the flash memory. 5.
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UM10360 NXP Semiconductors Chapter 5: LPC17xx Flash accelerator 5.2.2 Flash programming Issues Since the flash memory does not allow accesses during programming and erase operations, it is necessary for the flash accelerator to force the CPU to wait if a memory access to a flash address is requested while the flash memory is busy with a programming operation. Under some conditions, this delay could result in a Watchdog time-out.
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UM10360 NXP Semiconductors Chapter 5: LPC17xx Flash accelerator 5.4 Flash Accelerator Configuration register (FLASHCFG - 0x400F C000) Configuration bits select the flash access time, as shown in Table 49. The lower bits of FLASHCFG control internal flash accelerator functions and should not be altered. Following reset, flash accelerator functions are enabled and flash access timing is set to a default value of 4 clocks.
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UM10360 NXP Semiconductors Chapter 5: LPC17xx Flash accelerator If a flash instruction fetch and a flash data access from the CPU occur at the same time, the multilayer matrix gives precedence to the data access. This is because a stalled data access always slows down execution, while a stalled instruction fetch often does not. When the flash data access is concluded, any flash fetch or prefetch that had been in progress is re-initiated.
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UM10360 Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC) Rev. 2 — 19 August 2010 User manual 6.
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UM10360 NXP Semiconductors Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC) Table 50.
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UM10360 NXP Semiconductors Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC) Table 50.
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UM10360 NXP Semiconductors Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC) 6.4 Vector table remapping The Cortex-M3 incorporates a mechanism that allows remapping the interrupt vector table to alternate locations in the memory map. This is controlled via the Vector Table Offset Register (VTOR) contained in the Cortex-M3. The vector table may be located anywhere within the bottom 1 GB of Cortex-M3 address space.
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UM10360 NXP Semiconductors Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC) 6.5 Register description The following table summarizes the registers in the NVIC as implemented in the LPC17xx. The Cortex-M3 User Guide Section 34.4.2 provides a functional description of the NVIC. Table 51. Name NVIC register map Description Access Reset value Address ISER0 to Interrupt Set-Enable Registers.
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UM10360 NXP Semiconductors Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC) 6.5.1 Interrupt Set-Enable Register 0 register (ISER0 - 0xE000 E100) The ISER0 register allows enabling the first 32 peripheral interrupts, or for reading the enabled state of those interrupts. The remaining interrupts are enabled via the ISER1 register (Section 6.5.2). Disabling interrupts is done through the ICER0 and ICER1 registers (Section 6.5.3 and Section 6.5.4). Table 52.
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UM10360 NXP Semiconductors Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC) 6.5.2 Interrupt Set-Enable Register 1 register (ISER1 - 0xE000 E104) The ISER1 register allows enabling the second group of peripheral interrupts, or for reading the enabled state of those interrupts. Disabling interrupts is done through the ICER0 and ICER1 registers (Section 6.5.3 and Section 6.5.4). Table 53.
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UM10360 NXP Semiconductors Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC) 6.5.3 Interrupt Clear-Enable Register 0 (ICER0 - 0xE000 E180) The ICER0 register allows disabling the first 32 peripheral interrupts, or for reading the enabled state of those interrupts. The remaining interrupts are disabled via the ICER1 register (Section 6.5.4). Enabling interrupts is done through the ISER0 and ISER1 registers (Section 6.5.1 and Section 6.5.2). Table 54.
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UM10360 NXP Semiconductors Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC) 6.5.4 Interrupt Clear-Enable Register 1 register (ICER1 - 0xE000 E184) The ICER1 register allows disabling the second group of peripheral interrupts, or for reading the enabled state of those interrupts. Enabling interrupts is done through the ISER0 and ISER1 registers (Section 6.5.1 and Section 6.5.2). Table 55.
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UM10360 NXP Semiconductors Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC) 6.5.5 Interrupt Set-Pending Register 0 register (ISPR0 - 0xE000 E200) The ISPR0 register allows setting the pending state of the first 32 peripheral interrupts, or for reading the pending state of those interrupts. The remaining interrupts can have their pending state set via the ISPR1 register (Section 6.5.6). Clearing the pending state of interrupts is done through the ICPR0 and ICPR1 registers (Section 6.5.
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UM10360 NXP Semiconductors Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC) 6.5.6 Interrupt Set-Pending Register 1 register (ISPR1 - 0xE000 E204) The ISPR1 register allows setting the pending state of the second group of peripheral interrupts, or for reading the pending state of those interrupts. Clearing the pending state of interrupts is done through the ICPR0 and ICPR1 registers (Section 6.5.7 and Section 6.5.8). Table 57.
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UM10360 NXP Semiconductors Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC) 6.5.7 Interrupt Clear-Pending Register 0 register (ICPR0 - 0xE000 E280) The ICPR0 register allows clearing the pending state of the first 32 peripheral interrupts, or for reading the pending state of those interrupts. The remaining interrupts can have their pending state cleared via the ICPR1 register (Section 6.5.8). Setting the pending state of interrupts is done through the ISPR0 and ISPR1 registers (Section 6.5.
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UM10360 NXP Semiconductors Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC) 6.5.8 Interrupt Clear-Pending Register 1 register (ICPR1 - 0xE000 E284) The ICPR1 register allows clearing the pending state of the second group of peripheral interrupts, or for reading the pending state of those interrupts. Setting the pending state of interrupts is done through the ISPR0 and ISPR1 registers (Section 6.5.5 and Section 6.5.6). Table 59.
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UM10360 NXP Semiconductors Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC) 6.5.9 Interrupt Active Bit Register 0 (IABR0 - 0xE000 E300) The IABR0 register is a read-only register that allows reading the active state of the first 32 peripheral interrupts. This allows determining which peripherals are asserting an interrupt to the NVIC, and may also be pending if there are enabled. The remaining interrupts can have their active state read via the IABR1 register (Section 6.5.10). Table 60.
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UM10360 NXP Semiconductors Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC) 6.5.10 Interrupt Active Bit Register 1 (IABR1 - 0xE000 E304) The IABR1 register is a read-only register that allows reading the active state of the second group of peripheral interrupts. This allows determining which peripherals are asserting an interrupt to the NVIC, and may also be pending if there are enabled. Table 61.
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UM10360 NXP Semiconductors Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC) 6.5.11 Interrupt Priority Register 0 (IPR0 - 0xE000 E400) The IPR0 register controls the priority of the first 4 peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest priority. Table 62. Interrupt Priority Register 0 (IPR0 - 0xE000 E400) Bit Name Function 2:0 Unimplemented These bits ignore writes, and read as 0. 7:3 IP_WDT Watchdog Timer Interrupt Priority.
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UM10360 NXP Semiconductors Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC) 6.5.14 Interrupt Priority Register 3 (IPR3 - 0xE000 E40C) The IPR3 register controls the priority of the fourth group of 4 peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest priority. Table 65. Interrupt Priority Register 3 (IPR3 - 0xE000 E40C) Bit Name Function 2:0 Unimplemented These bits ignore writes, and read as 0. 7:3 IP_I2C2 I2C2 Interrupt Priority.
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UM10360 NXP Semiconductors Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC) 6.5.17 Interrupt Priority Register 6 (IPR6 - 0xE000 E418) The IPR6 register controls the priority of the seventh group of 4 peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest priority. Table 68. Interrupt Priority Register 6 (IPR6 - 0xE000 E418) Bit Name Function 2:0 Unimplemented These bits ignore writes, and read as 0. 7:3 IP_USB USB Interrupt Priority.
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UM10360 NXP Semiconductors Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC) 6.5.20 Software Trigger Interrupt Register (STIR - 0xE000 EF00) The STIR register provides an alternate way for software to generate an interrupt, in addition to using the ISPR registers. This mechanism can only be used to generate peripheral interrupts, not system exceptions. By default, only privileged software can write to the STIR register.
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UM10360 Chapter 7: LPC17xx Pin configuration Rev. 2 — 19 August 2010 User manual 76 100 7.1 LPC17xx pin configuration 25 51 50 75 26 1 002aad945_1 61 80 Fig 14. LPC176x LQFP100 pin configuration 20 41 40 60 21 1 002aae158 Fig 15. LPC175x LQFP80 pin configuration UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 August 2010 © NXP B.V. 2010. All rights reserved.
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UM10360 NXP Semiconductors Chapter 7: LPC17xx Pin configuration ball A1 index area LPC1768FET100 1 2 3 4 5 6 7 8 9 10 A B C D E F G H J K 002aaf723 Transparent top view Fig 16. Pin configuration TFBGA100 package Table 72.
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UM10360 NXP Semiconductors Chapter 7: LPC17xx Pin configuration Table 72.
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UM10360 NXP Semiconductors Chapter 7: LPC17xx Pin configuration Table 72.
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UM10360 NXP Semiconductors Chapter 7: LPC17xx Pin configuration Table 73.
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UM10360 NXP Semiconductors Chapter 7: LPC17xx Pin configuration Table 73. Pin description …continued Symbol LQFP 100 P0[8] / I2STX_WS / 77 MISO1 / MAT2[2] P0[9] / 76 LQFP 80 Type Description 62 I/O P0[8] — General purpose digital input/output pin. I/O I2STX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S bus specification. I/O MISO1 — Master In Slave Out for SSP1.
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UM10360 NXP Semiconductors Chapter 7: LPC17xx Pin configuration Table 73. Pin description …continued Symbol LQFP 100 LQFP 80 Type Description P0[20] / DTR1 / SCL1 58 - I/O P0[20] — General purpose digital input/output pin. O DTR1 — Data Terminal Ready output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal. I/O SCL1 — I2C1 clock input/output (this pin does not use a specialized I2C pad, see Section 19.1 for details).
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UM10360 NXP Semiconductors Chapter 7: LPC17xx Pin configuration Table 73. Pin description …continued Symbol LQFP 100 LQFP 80 Type Description P0[28] / SCL0 / USB_SCL 24 - I/O P0[28] — General purpose digital input/output pin. Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus specifications for 100 kHz standard mode, 400 kHz Fast Mode, and 1 MHz Fast Mode Plus. This pad requires an external pull-up to provide output functionality.
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UM10360 NXP Semiconductors Chapter 7: LPC17xx Pin configuration Table 73. Pin description …continued Symbol LQFP 100 P1[18] / 32 USB_UP_LED / PWM1[1] / CAP1[0] P1[19] / MCOA0 / USB_PPWR / CAP1[1] 33 P1[20] / MCI0 / PWM1[2] / SCK0 34 P1[21] / 35 LQFP 80 Type Description 25 I/O P1[18] — General purpose digital input/output pin. O USB_UP_LED — USB GoodLink LED indicator. It is LOW when device is configured (non-control endpoints enabled).
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UM10360 NXP Semiconductors Chapter 7: LPC17xx Pin configuration Table 73. Pin description …continued Symbol LQFP 100 LQFP 80 Type Description P1[27] / CLKOUT / USB_OVRCR / CAP0[1] 43 - I/O P1[27] — General purpose digital input/output pin. P1[28] / MCOA2 / 44 PCAP1[0] / MAT0[0] P1[29] / MCOB2 / PCAP1[1] / MAT0[1] P1[30] / VBUS / AD0[4] 45 21 35 36 18 O CLKOUT — Clock output pin. I USB_OVRCR — USB port Over-Current status. I CAP0[1] — Capture input for Timer 0, channel 1.
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UM10360 NXP Semiconductors Chapter 7: LPC17xx Pin configuration Table 73. Pin description …continued Symbol LQFP 100 LQFP 80 Type Description P2[4] / PWM1[5] / DSR1 / TRACEDATA[1] 69 54 I/O P2[4] — General purpose digital input/output pin.
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UM10360 NXP Semiconductors Chapter 7: LPC17xx Pin configuration Table 73. Pin description …continued Symbol LQFP 100 LQFP 80 Type Description P2[12] / EINT2 / I2STX_WS 51 - I/O P2[12] — General purpose digital input/output pin. 5 V tolerant pad with 5 ns glitch filter providing digital I/O functions with TTL levels and hysteresis. I EINT2 — External interrupt 2 input. I/O I2STX_WS — Transmit Word Select. It is driven by the master and received by the slave.
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UM10360 NXP Semiconductors Chapter 7: LPC17xx Pin configuration Table 73. Pin description …continued Symbol LQFP 100 LQFP 80 Type Description RSTOUT 14 11 O RSTOUT — This is a 3.3 V pin. A LOW output on this pin indicates that the device is in the reset state, for any reason. This reflects the RESET input pin and all internal reset sources.
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UM10360 Chapter 8: LPC17xx Pin connect block Rev. 2 — 19 August 2010 User manual 8.1 How to read this chapter Table 74 shows the functions of the PINSEL registers in the LPC17xx. Table 74.
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UM10360 NXP Semiconductors Chapter 8: LPC17xx Pin connect block The direction control bit in the GPIO registers is effective only when the GPIO function is selected for a pin. For other functions, direction is controlled automatically. Each derivative typically has a different pinout and therefore a different set of functions possible for each pin. Details for a specific derivative may be found in the appropriate data sheet.
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UM10360 NXP Semiconductors Chapter 8: LPC17xx Pin connect block Function of PINMODE in open drain mode Normally the value of PINMODE applies to a pin only when it is in the input mode. When a pin is in the open drain mode, caused by a 1 in the corresponding bit of one of the PINMODE_OD registers, the input mode still does not apply when the pin is outputting a 0. However, when the pin value is 1, PINMODE applies since this state turns off the pin’s output driver.
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UM10360 NXP Semiconductors Chapter 8: LPC17xx Pin connect block 8.5 Register description The Pin Control Module contains 11 registers as shown in Table 78 below. Table 78. Pin Connect Block Register Map Name Description Access Reset Value[1] Address PINSEL0 Pin function select register 0. R/W 0 0x4002 C000 PINSEL1 Pin function select register 1. R/W 0 0x4002 C004 PINSEL2 Pin function select register 2. R/W 0 0x4002 C008 PINSEL3 Pin function select register 3.
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UM10360 NXP Semiconductors Chapter 8: LPC17xx Pin connect block 8.5.1 Pin Function Select register 0 (PINSEL0 - 0x4002 C000) The PINSEL0 register controls the functions of the lower half of Port 0. The direction control bit in FIO0DIR register is effective only when the GPIO function is selected for a pin. For other functions, the direction is controlled automatically. Table 79.
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UM10360 NXP Semiconductors Chapter 8: LPC17xx Pin connect block Table 80. Pin function select register 1 (PINSEL1 - address 0x4002 C004) bit description PINSEL1 Pin name Function when Function 00 when 01 27:26 P0.29 GPIO Port 0.29 USB_D+ Function when 10 Function when 11 Reset value Reserved Reserved 00 29:28 P0.30 GPIO Port 0.30 USB_D− Reserved Reserved 00 31:30 - Reserved Reserved Reserved Reserved 00 [1] Not available on 80-pin package.
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UM10360 NXP Semiconductors Chapter 8: LPC17xx Pin connect block Table 82. Pin function select register 3 (PINSEL3 - address 0x4002 C00C) bit description PINSEL3 Pin name Function when Function when 00 01 Function when 10 Function when 11 Reset value 15:14 GPIO Port 1.23 MCI1 PWM1.4 MISO0 00 P1.23 17:16 P1.24 GPIO Port 1.24 MCI2 PWM1.5 MOSI0 00 19:18 P1.25 GPIO Port 1.25 MCOA1 Reserved MAT1.1 00 21:20 P1.26 GPIO Port 1.26 MCOB1 PWM1.6 CAP0.0 00 23:22 P1.27[1] GPIO Port 1.
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UM10360 NXP Semiconductors Chapter 8: LPC17xx Pin connect block 8.5.6 Pin Function Select Register 7 (PINSEL7 - 0x4002 C01C) The PINSEL7 register controls the functions of the upper half of Port 3. The direction control bit in the FIO3DIR register is effective only when the GPIO function is selected for a pin. For other functions, direction is controlled automatically. Table 84.
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UM10360 NXP Semiconductors Chapter 8: LPC17xx Pin connect block 8.5.9 Pin Mode select register 0 (PINMODE0 - 0x4002 C040) This register controls pull-up/pull-down resistor configuration for Port 0 pins 0 to 15. Table 87. Pin Mode select register 0 (PINMODE0 - address 0x4002 C040) bit description PINMODE0 Symbol 1:0 Value P0.00MODE Description Reset value Port 0 pin 0 on-chip pull-up/down resistor control. 00 00 P0.0 pin has a pull-up resistor enabled. 01 P0.0 pin has repeater mode enabled.
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UM10360 NXP Semiconductors Chapter 8: LPC17xx Pin connect block Table 88. Pin Mode select register 1 (PINMODE1 - address 0x4002 C044) bit description PINMODE1 Symbol Description Reset value 21:20 Port 1 pin 26 control, see P0.00MODE. 00 P0.26MODE 29:22 - Reserved. 31:30 - Reserved. [2] NA NA [1] Not available on 80-pin package. [2] The pin mode cannot be selected for pins P0[27] to P0[30]. Pins P0[27] and P0[28] are dedicated I2C open-drain pins without pull-up/down.
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UM10360 NXP Semiconductors Chapter 8: LPC17xx Pin connect block Table 90. Pin Mode select register 3 (PINMODE3 - address 0x4002 C04C) bit description PINMODE3 Symbol Description Reset value 15:14 P1.23MODE Port 1 pin 23 control, see P0.00MODE. 00 17:16 P1.24MODE Port 1 pin 24 control, see P0.00MODE. 00 19:18 P1.25MODE Port 1 pin 25 control, see P0.00MODE. 00 21:20 P1.26MODE Port 1 pin 26 control, see P0.00MODE. 00 23:22 P1.27MODE[1] Port 1 pin 27 control, see P0.00MODE.
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UM10360 NXP Semiconductors Chapter 8: LPC17xx Pin connect block 8.5.14 Pin Mode select register 7 (PINMODE7 - 0x4002 C05C) This register controls pull-up/pull-down resistor configuration for Port 3 pins 16 to 31. For details see Section 8.4 “Pin mode select register values”. Table 92. Pin Mode select register 7 (PINMODE7 - address 0x4002 C05C) bit description PINMODE7 Symbol Description Reset value 17:0 - Reserved NA 19:18 P3.25MODE[1] Port 3 pin 25 control, see P0.00MODE. 00 21:20 P3.
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UM10360 NXP Semiconductors Chapter 8: LPC17xx Pin connect block Table 94. Open Drain Pin Mode select register 0 (PINMODE_OD0 - address 0x4002 C068) bit description PINMODE Symbol _OD0 Value Description Reset value 10 P0.10OD[3] Port 0 pin 10 open drain mode control, see P0.00OD 0 11 P0.11OD[3] Port 0 pin 11 open drain mode control, see P0.00OD 0 14:12 - Reserved. NA 15 P0.15OD Port 0 pin 15 open drain mode control, see P0.00OD 0 16 P0.
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UM10360 NXP Semiconductors Chapter 8: LPC17xx Pin connect block Table 95. Open Drain Pin Mode select register 1 (PINMODE_OD1 - address 0x4002 C06C) bit description PINMODE Symbol _OD1 Value Description Reset value 7:5 - Reserved. NA 8 P1.08OD Port 1 pin 8 open drain mode control, see P1.00OD 0 9 P1.09OD Port 1 pin 9 open drain mode control, see P1.00OD 0 10 P1.10OD Port 1 pin 10 open drain mode control, see P1.00OD 0 13:11 - Reserved. NA 14 P1.
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UM10360 NXP Semiconductors Chapter 8: LPC17xx Pin connect block Table 96. Open Drain Pin Mode select register 2 (PINMODE_OD2 - address 0x4002 C070) bit description PINMODE Symbol _OD2 Value Description Reset value 5 P2.05OD Port 2 pin 5 open drain mode control, see P2.00OD 0 6 P2.06OD Port 2 pin 6 open drain mode control, see P2.00OD 0 7 P2.07OD Port 2 pin 7 open drain mode control, see P2.00OD 0 8 P2.08OD Port 2 pin 8 open drain mode control, see P2.00OD 0 9 P2.
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UM10360 NXP Semiconductors Chapter 8: LPC17xx Pin connect block Table 98. Open Drain Pin Mode select register 4 (PINMODE_OD4 - address 0x4002 C078) bit description PINMODE Symbol _OD4 28 Value Description P4.28OD Reset value Port 4 pin 28 open drain mode control. 0 0 P4.28 pin is in the normal (not open drain) mode. 1 P4.28 pin is in the open drain mode. 29 P4.28OD Port 4 pin 29 open drain mode control, see P4.28OD 0 31:30 - Reserved. NA 8.5.
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UM10360 Chapter 9: LPC17xx General Purpose Input/Output (GPIO) Rev. 2 — 19 August 2010 User manual 9.1 Basic configuration GPIOs are configured using the following registers: 1. Power: always enabled. 2. Pins: See Section 8.3 for GPIO pins and their modes. 3. Wake-up: GPIO ports 0 and 2 can be used for wake-up if needed, see (Section 4.8.8). 4. Interrupts: Enable GPIO interrupts in IO0/2IntEnR (Table 114) or IO0/2IntEnF (Table 116).
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UM10360 NXP Semiconductors Chapter 9: LPC17xx General Purpose Input/Output (GPIO) • Registers provide a software view of pending rising edge interrupts, pending falling edge interrupts, and overall pending GPIO interrupts. • GPIO0 and GPIO2 interrupts share the same position in the NVIC with External Interrupt 3. 9.
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UM10360 NXP Semiconductors Chapter 9: LPC17xx General Purpose Input/Output (GPIO) 9.5 Register description Due to compatibility requirements with the LPC2300 series ARM7-based products, the LPC17xx implements portions of five 32-bit General Purpose I/O ports. Details on a specific GPIO port usage can be found in Section 8.3. The registers in Table 101 represent the enhanced GPIO features available on all of the GPIO ports. These registers are located on an AHB bus for fast read and write timing.
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UM10360 NXP Semiconductors Chapter 9: LPC17xx General Purpose Input/Output (GPIO) Table 102. GPIO interrupt register map Generic Name Description Access Reset value[1] PORTn Register Name & Address IntEnR GPIO Interrupt Enable for Rising edge. R/W 0 IO0IntEnR - 0x4002 8090 IO2IntEnR - 0x4002 80B0 IntEnF GPIO Interrupt Enable for Falling edge. R/W 0 IO0IntEnR - 0x4002 8094 IO2IntEnR - 0x4002 80B4 IntStatR GPIO Interrupt Status for Rising edge.
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UM10360 NXP Semiconductors Chapter 9: LPC17xx General Purpose Input/Output (GPIO) Table 104. Fast GPIO port Direction control byte and half-word accessible register description Generic Register name Description FIOxDIR0 Register length (bits) & access Reset value PORTn Register Address & Name Fast GPIO Port x Direction 8 (byte) control register 0. Bit 0 in R/W FIOxDIR0 register corresponds to pin Px.0 … bit 7 to pin Px.7.
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UM10360 NXP Semiconductors Chapter 9: LPC17xx General Purpose Input/Output (GPIO) Access to a port pin via the FIOxSET register is conditioned by the corresponding bit of the FIOxMASK register (see Section 9.5.5). Table 105. Fast GPIO port output Set register (FIO0SET to FIO4SET - addresses 0x2009 C018 to 0x2009 C098) bit description Bit Symbol Value Description 31:0 FIO0SET FIO1SET FIO2SET 0 FIO3SET FIO4SET 1 Reset value Fast GPIO output value Set bits. Bit 0 in FIOxSET controls pin Px.
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UM10360 NXP Semiconductors Chapter 9: LPC17xx General Purpose Input/Output (GPIO) 9.5.3 GPIO port output Clear register FIOxCLR (FIO0CLR to FIO4CLR0x2009 C01C to 0x2009 C09C) This register is used to produce a LOW level output at port pins configured as GPIO in an OUTPUT mode. Writing 1 produces a LOW level at the corresponding port pin and clears the corresponding bit in the FIOxSET register. Writing 0 has no effect.
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UM10360 NXP Semiconductors Chapter 9: LPC17xx General Purpose Input/Output (GPIO) Table 108. Fast GPIO port output Clear byte and half-word accessible register description Generic Register name Description Register length (bits) & access Reset value PORTn Register Address & Name FIOxCLR3 Fast GPIO Port x output Clear register 3. Bit 0 in FIOxCLR3 register corresponds to pin Px.24 … bit 7 to pin Px.31.
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UM10360 NXP Semiconductors Chapter 9: LPC17xx General Purpose Input/Output (GPIO) Only pins masked with zeros in the Mask register (see Section 9.5.5) will be correlated to the current content of the Fast GPIO port pin value register. Table 109. Fast GPIO port Pin value register (FIO0PIN to FIO4PIN- addresses 0x2009 C014 to 0x2009 C094) bit description Bit Symbol 31:0 FIO0VAL FIO1VAL FIO2VAL FIO3VAL FIO4VAL Value Description Reset value Fast GPIO output value bits. Bit 0 corresponds to pin Px.
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UM10360 NXP Semiconductors Chapter 9: LPC17xx General Purpose Input/Output (GPIO) Table 110. Fast GPIO port Pin value byte and half-word accessible register description Generic Register name Description Register length (bits) & access Reset value PORTn Register Address & Name FIOxPIN3 Fast GPIO Port x Pin value register 3. Bit 0 in FIOxPIN3 register corresponds to pin Px.24 … bit 7 to pin Px.31.
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UM10360 NXP Semiconductors Chapter 9: LPC17xx General Purpose Input/Output (GPIO) Aside from the 32-bit long and word only accessible FIOxMASK register, every fast GPIO port can also be controlled via several byte and half-word accessible registers listed in Table 112, too. Next to providing the same functions as the FIOxMASK register, these additional registers allow easier and faster access to the physical port pins. Table 112.
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UM10360 NXP Semiconductors Chapter 9: LPC17xx General Purpose Input/Output (GPIO) 9.5.6 GPIO interrupt registers The following registers configure the pins of Port 0 and Port 2 to generate interrupts. 9.5.6.1 GPIO overall Interrupt Status register (IOIntStatus - 0x4002 8080) This read-only register indicates the presence of interrupt pending on all of the GPIO ports that support GPIO interrupts. Only status one bit per port is required. Table 113.
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UM10360 NXP Semiconductors Chapter 9: LPC17xx General Purpose Input/Output (GPIO) Table 114. GPIO Interrupt Enable for port 0 Rising Edge (IO0IntEnR - 0x4002 8090) bit description Bit Symbol Value Description Reset value 17 P0.17ER Enable rising edge interrupt for P0.17. 0 18 P0.18ER Enable rising edge interrupt for P0.18. 0 19 P0.19ER[1] Enable rising edge interrupt for P0.19. 0 20 P0.20ER[1] Enable rising edge interrupt for P0.20. 0 21 P0.
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UM10360 NXP Semiconductors Chapter 9: LPC17xx General Purpose Input/Output (GPIO) Table 115. GPIO Interrupt Enable for port 2 Rising Edge (IO2IntEnR - 0x4002 80B0) bit description Bit Symbol Value Description 12 P2.12ER[1] Enable rising edge interrupt for P2.12. 0 13 P2.13ER[1] Enable rising edge interrupt for P2.13. 0 Reserved. NA 31:14 [1] Reset value Not available on 80-pin package. 9.5.6.
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UM10360 NXP Semiconductors Chapter 9: LPC17xx General Purpose Input/Output (GPIO) Table 116. GPIO Interrupt Enable for port 0 Falling Edge (IO0IntEnF - address 0x4002 8094) bit description Bit Symbol 28 P0.28EF[1] Enable falling edge interrupt for P0.28. 0 29 P0.29EF Enable falling edge interrupt for P0.29. 0 30 P0.30EF Enable falling edge interrupt for P0.30. 0 31 - Reserved. NA [1] Value Description Reset value Not available on 80-pin package. 9.5.6.
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UM10360 NXP Semiconductors Chapter 9: LPC17xx General Purpose Input/Output (GPIO) 9.5.6.6 GPIO Interrupt Status for port 0 Rising Edge Interrupt (IO0IntStatR 0x4002 8084) Each bit in these read-only registers indicates the rising edge interrupt status for port 0. Table 118. GPIO Interrupt Status for port 0 Rising Edge Interrupt (IO0IntStatR - 0x4002 8084) bit description Bit Symbol 0 P0.0REI User manual Reset value Status of Rising Edge Interrupt for P0.
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UM10360 NXP Semiconductors Chapter 9: LPC17xx General Purpose Input/Output (GPIO) 9.5.6.7 GPIO Interrupt Status for port 2 Rising Edge Interrupt (IO2IntStatR 0x4002 80A4) Each bit in these read-only registers indicates the rising edge interrupt status for port 2. Table 119. GPIO Interrupt Status for port 2 Rising Edge Interrupt (IO2IntStatR - 0x4002 80A4) bit description Bit Symbol 0 P2.0REI Value Description Reset value Status of Rising Edge Interrupt for P2.
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UM10360 NXP Semiconductors Chapter 9: LPC17xx General Purpose Input/Output (GPIO) Table 120. GPIO Interrupt Status for port 0 Falling Edge Interrupt (IO0IntStatF - 0x4002 8088) bit description Bit Symbol Value Description Reset value 8 P0.8FEI Status of Falling Edge Interrupt for P0.8. 0 9 P0.9FEI Status of Falling Edge Interrupt for P0.9. 0 10 P0.10FEI Status of Falling Edge Interrupt for P0.10. 0 11 P0.11FEI Status of Falling Edge Interrupt for P0.11. 0 14:12 - Reserved.
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UM10360 NXP Semiconductors Chapter 9: LPC17xx General Purpose Input/Output (GPIO) Table 121. GPIO Interrupt Status for port 2 Falling Edge Interrupt (IO2IntStatF - 0x4002 80A8) bit description Bit Symbol Value Description 7 P2.7FEI Status of Falling Edge Interrupt for P2.7. 0 8 P2.8FEI Status of Falling Edge Interrupt for P2.8. 0 9 P2.9FEI Status of Falling Edge Interrupt for P2.9. 0 10 P2.10FEI Status of Falling Edge Interrupt for P2.10. 0 11 P2.
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UM10360 NXP Semiconductors Chapter 9: LPC17xx General Purpose Input/Output (GPIO) Table 122. GPIO Interrupt Clear register for port 0 (IO0IntClr - 0x4002 808C)) bit description Bit Symbol 23 P0.23CI[1] 24 P0.24CI[1] Clear GPIO port Interrupts for P0.24. 0 25 P0.25CI Clear GPIO port Interrupts for P0.25. 0 26 P0.26CI Clear GPIO port Interrupts for P0.26. 0 27 P0.27CI[1] Clear GPIO port Interrupts for P0.27. 0 28 P0.28CI[1] Clear GPIO port Interrupts for P0.28. 0 29 P0.
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UM10360 NXP Semiconductors Chapter 9: LPC17xx General Purpose Input/Output (GPIO) 9.6 GPIO usage notes 9.6.1 Example: An instantaneous output of 0s and 1s on a GPIO port Solution 1: using 32-bit (word) accessible fast GPIO registers FIO0MASK = 0xFFFF00FF ; FIO0PIN = 0x0000A500; Solution 2: using 16-bit (half-word) accessible fast GPIO registers FIO0MASKL = 0x00FF; FIO0PINL = 0xA500; Solution 3: using 8-bit (byte) accessible fast GPIO registers FIO0PIN1 = 0xA5; 9.6.2 Writing to FIOSET/FIOCLR vs.
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UM10360 Chapter 10: LPC17xx Ethernet Rev. 2 — 19 August 2010 User manual 10.1 Basic configuration The Ethernet controller is configured using the following registers: 1. Power: In the PCONP register (Table 46), set bit PCENET. Remark: On reset, the Ethernet block is disabled (PCENET = 0). 2. Clock: see Table 38. 3. Pins: Enable Ethernet pins through the PINSEL registers and select their modes through the PINMODE registers, see Section 8.5. 4.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet Table 124. Ethernet acronyms, abbreviations, and definitions Acronym or Abbreviation Definition Frame An Ethernet frame consists of destination address, source address, length type field, payload and frame check sequence. Half-word 16-bit entity LAN Local Area Network MAC Media Access Control sublayer MII Media Independent Interface MIIM MII management Octet An 8-bit data entity, used in lieu of "byte" by IEEE 802.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet – Over-length frame support for both transmit and receive allows any length frames. – Promiscuous receive mode. – Automatic collision backoff and frame retransmission. – Includes power management by clock switching. – Wake-on-LAN power management support allows system wake-up: using the receive filters or a magic frame detection filter. • Physical interface: – Attachment of external PHY chip through a standard Reduced MII (RMII) interface.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet – The transmit DMA manager which reads descriptors and data from memory and writes status to memory. – The transmit retry module handling Ethernet retry and abort situations. – The transmit flow control module which can insert Ethernet pause frames. • The receive data path, including: – The receive DMA manager which reads descriptors from memory and writes data and status to memory.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet Hardware in the DMA engine controls how data incoming from the Ethernet MAC is saved to memory, causes fragment related status to be saved, and advances the hardware receive pointer for incoming data. Driver software must handle the disposition of received data, changing of descriptor data addresses (to avoid unnecessary data movement), and advancing the software receive pointer.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet The Ethernet frame consists of the destination address, the source address, an optional VLAN field, the length/type field, the payload and the frame check sequence. Each address consists of 6 bytes where each byte consists of 8 bits. Bits are transferred starting with the least significant bit. 10.8 Overview 10.8.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet Support for IEEE 802.3/clause 31 flow control is implemented in the flow control block. Receive flow control frames are automatically handled by the MAC. Transmit flow control frames can be initiated by software. In half duplex mode, the flow control module will generate back pressure by sending out continuous preamble only, interrupted by pauses to prevent the jabber limit from being exceeded.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet 10.10 Registers and software interface The software interface of the Ethernet block consists of a register view and the format definitions for the transmit and receive descriptors. These two aspects are addressed in the next two subsections. 10.10.1 Register map Table 128 lists the registers, register addresses and other basic information. The total AHB address space required is 4 kilobytes.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet Table 128. Ethernet register definitions Name Description Access Reset Value Address Status Status register. RO 0 0x5000 0104 RxDescriptor Receive descriptor base address register. R/W 0 0x5000 0108 RxStatus Receive status base address register. R/W 0 0x5000 010C RxDescriptorNumber Receive number of descriptors register. R/W 0 0x5000 0110 RxProduceIndex Receive produce index register.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet 10.11 Ethernet MAC register definitions This section defines the bits in the individual registers of the Ethernet block register map. 10.11.1 MAC Configuration Register 1 (MAC1 - 0x5000 0000) The MAC configuration register 1 (MAC1) has an address of 0x5000 0000. Its bit definition is shown in Table 129. Table 129.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet Table 130. MAC Configuration register 2 (MAC2 - address 0x5000 0004) bit description Bit Symbol Function Reset value 0 FULL-DUPLEX When enabled (set to ’1’), the MAC operates in Full-Duplex mode. When disabled, the MAC operates in Half-Duplex mode. 0 1 FRAME LENGTH CHECKING When enabled (set to ’1’), both transmit and receive frame lengths are compared to 0 the Length/Type field.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet Table 131. Pad operation Type Auto detect VLAN pad pad enable enable MAC2 [7] MAC2 [6] Pad/CRC enable MAC2 [5] Action Any x x 0 No pad or CRC check Any 0 0 1 Pad to 60 bytes, append CRC Any x 1 1 Pad to 64 bytes, append CRC Any 1 0 1 If untagged, pad to 60 bytes and append CRC. If VLAN tagged: pad to 64 bytes and append CRC. 10.11.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet 10.11.5 Collision Window / Retry Register (CLRT - 0x5000 0010) The Collision window / Retry register (CLRT) has an address of 0x5000 0010. Its bit definition is shown in Table 134. Table 134.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet Table 137. Test register (TEST - address 0x5000 ) bit description Bit Symbol Function Reset value 0 SHORTCUT PAUSE QUANTA This bit reduces the effective PAUSE quanta from 64 byte-times to 1 byte-time. 0 1 TEST PAUSE This bit causes the MAC Control sublayer to inhibit transmissions, just as if a 0 PAUSE Receive Control frame with a nonzero pause time parameter was received.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet Table 139. Clock select encoding Clock Select Bit 5 Bit 4 Bit 3 Bit 2 Maximum AHB clock supported Host Clock divided by 48 1 0 1 1 120[1] Host Clock divided by 52 1 1 0 0 130[1] Host Clock divided by 56 1 1 0 1 140[1] Host Clock divided by 60 1 1 1 0 150[1] Host Clock divided by 64 1 1 1 1 160[1] [1] The maximum AHB clock rate allowed is limited to the maximum CPU clock rate for the device. 10.11.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet Table 142. MII Mgmt Write Data register (MWTD - address 0x5000 002C) bit description Bit Symbol Function Reset value 15:0 WRITE DATA When written, an MII Mgmt write cycle is performed using the 16-bit data and the pre-configured PHY and Register addresses from the MII Mgmt Address register (MADR). 0x0 31:16 - Unused 0x0 10.11.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet 3. Wait for busy bit to be cleared in MIND 4. Write 0 to MCMD 5. Read data from MRDD 10.11.15 Station Address 0 Register (SA0 - 0x5000 0040) The Station Address 0 register (SA0) has an address of 0x5000 0040. The bit definition of this register is shown in Table 145. Table 145.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet The station address is used for perfect address filtering and for sending pause control frames. For the ordering of the octets in the packet please refer to Figure 18. 10.12 Control register definitions 10.12.1 Command Register (Command - 0x5000 0100) The Command register (Command) register has an address of 0x5000 0100. Its bit definition is shown in Table 148. Table 148.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet • It is enabled and the Rx/TxEnable bit is set in the Command register or it just got disabled while still transmitting or receiving a frame. • Also, for the transmit channel, the transmit queue is not empty i.e. ProduceIndex != ConsumeIndex. • Also, for the receive channel, the receive queue is not full i.e. ProduceIndex != ConsumeIndex - 1.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet Table 152. Receive Number of Descriptors register (RxDescriptor - address 0x5000 0110) bit description Bit Symbol Function Reset value 15:0 RxDescriptorNumber Number of descriptors in the descriptor array for which RxDescriptor is the base address. The number of descriptors is minus one encoded.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet of RxDescriptorNumber has been reached. If the RxProduceIndex equals RxConsumeIndex - 1, the array is full and any further frames being received will cause a buffer overrun error. 10.12.8 Transmit Descriptor Base Address Register (TxDescriptor 0x5000 011C) The Transmit Descriptor base address register (TxDescriptor) has an address of 0x5000 011C. Its bit definition is shown in Table 155. Table 155.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet The transmit number of descriptors register defines the number of descriptors in the descriptor array for which TxDescriptor is the base address. The number of descriptors should match the number of statuses. The register uses minus one encoding i.e. if the array has 8 elements, the value in the register should be 7. 10.12.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet distributed over two registers TSV0 and TSV1. These registers are provided for debug purposes, because the communication between driver software and the Ethernet block takes place primarily through the frame descriptors. The status register contents are valid as long as the internal status of the MAC is valid and should typically only be read when the transmit and receive processes are halted.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet purposes, because the communication between driver software and the Ethernet block takes place primarily through the frame descriptors. The status register contents are valid as long as the internal status of the MAC is valid and should typically only be read when the transmit and receive processes are halted.Table 161 lists the bit definitions of the TSV1 register. Table 161.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet Table 162. Receive Status Vector register (RSV - address 0x5000 0160) bit description Bit Symbol Function 26 Dribble Nibble Indicates that after the end of packet another 1-7 bits were 0 received. A single nibble, called dribble nibble, is formed but not sent out. 27 Control frame The frame was a control frame. 0 28 PAUSE The frame was a control frame with a valid PAUSE opcode.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet 10.13 Receive filter register definitions 10.13.1 Receive Filter Control Register (RxFilterCtrl - 0x5000 0200) The Receive Filter Control register (RxFilterCtrl) has an address of 0x5000 0200. Table 165 lists the definition of the individual bits in the register. Table 165.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet Table 166. Receive Filter WoL Status register (RxFilterWoLStatus - address 0x5000 0204) bit description Bit Symbol Function Reset value 6 - Unused 0x0 7 RxFilterWoL When the value is ’1’, the receive filter caused WoL. 0 8 MagicPacketWoL When the value is ’1’, the magic packet filter caused WoL. 0 Unused 0x0 31:9 - The bits in this register record the cause for a WoL.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet 10.13.5 Hash Filter Table MSBs Register (HashFilterH - 0x5000 0214) The Hash Filter table MSBs register (HashFilterH) has an address of 0x5000 0214. Table 169 lists the bit definitions of the register. Details of Hash filter table use can be found in Section 10.17.10 “Receive filtering” on page 198. Table 169.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet The interrupt status register is read-only. Setting can be done via the IntSet register. Reset can be accomplished via the IntClear register. 10.14.2 Interrupt Enable Register (IntEnable - 0x5000 0FE4) The Interrupt Enable register (IntEnable) has an address of 0x5000 0FE4. The interrupt enable register bit definition is shown in Table 171. Table 171.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet Table 172. Interrupt Clear register (IntClear - address 0x5000 0FE8) bit description Bit Symbol Function Reset value 0 RxOverrunIntClr 0 1 RxErrorIntClr 2 RxFinishedIntClr Writing a ’1’ to one of these bits clears (0 to 7) the corresponding status bit in interrupt status register IntStatus.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet 10.14.5 Power-Down Register (PowerDown - 0x5000 0FF4) The Power-Down register (PowerDown) is used to block all AHB accesses except accesses to the Power-Down register. The register has an address of 0x5000 0FF4. The bit definition of the register is listed in Table 174. Table 174.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet 10.15 Descriptor and status formats This section defines the descriptor format for the transmit and receive scatter/gather DMA engines. Each Ethernet frame can consist of one or more fragments. Each fragment corresponds to a single descriptor. The DMA managers in the Ethernet block scatter (for receive) and gather (for transmit) multiple fragments for a single Ethernet frame. 10.15.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet received. The RxConsumeIndex is programmed by software and is the index of the next descriptor that the software receive driver is going to process. When RxProduceIndex == RxConsumeIndex, the receive buffer is empty. When RxProduceIndex == RxConsumeIndex -1 (taking wraparound into account), the receive buffer is full and newly received data would generate an overflow unless the software driver frees up one or more descriptors.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet Table 178. Receive Status HashCRC Word Bit Symbol Description 8:0 SAHashCRC Hash CRC calculated from the source address. 15:9 - Unused 24:16 DAHashCRC Hash CRC calculated from the destination address. 31:25 - Unused The StatusInfo word contains flags returned by the MAC and flags generated by the receive data path reflecting the status of the reception. Table 179 lists the bit definitions in the StatusInfo word. Table 179.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet [1] The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Range" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet Two registers, TxConsumeIndex and TxProduceIndex, define the descriptor locations that will be used next by hardware and software. Both register act as counters starting at 0 and wrapping when they reach the value of TxDescriptorNumber. The TxProduceIndex contains the index of the next descriptor that is going to be filled by the software driver. The TxConsumeIndex contains the index of the next descriptor going to be transmitted by the hardware.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet The transmit status consists of one word which is the StatusInfo word. It contains flags returned by the MAC and flags generated by the transmit data path reflecting the status of the transmission. Table 183 lists the bit definitions in the StatusInfo word. Table 183. Transmit status information word Bit Symbol 20:0 - Description Unused 24:21 CollisionCount The number of collisions this packet incurred, up to the Retransmission Maximum.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet To transmit a packet the software driver has to set up the appropriate Control registers and a descriptor to point to the packet data buffer before transferring the packet to hardware by incrementing the TxProduceIndex register. After transmission, hardware will increment TxConsumeIndex and optionally generate an interrupt. The hardware will receive packets from the PHY and apply filtering as configured by the software driver.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet The Ethernet block includes two DMA managers. The DMA managers make it possible to transfer frames directly to and from memory with little support from the processor and without the need to trigger an interrupt for each frame. The DMA managers work with arrays of frame descriptors and statuses that are stored in memory. The descriptors and statuses act as an interface between the Ethernet hardware and the device driver software.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet the one at the next higher, adjacent memory address. Wrap around means that when the Ethernet block has finished reading/writing the last descriptor/status of the array (with the highest memory address), the next descriptor/status it reads/writes is the first descriptor/status of the array at the base address of the array. Full and Empty state of descriptor arrays The descriptor arrays can be empty, partially full or full.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet to a fragment of a frame. By using fragments, scatter/gather DMA can be done: transmit frames are gathered from multiple fragments in memory and receive frames can be scattered to multiple fragments in memory. By stringing together fragments it is possible to create large frames from small memory areas.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet Please note that the transmit descriptors, receive descriptors and receive statuses are 8 bytes each while the transmit statuses are 4 bytes each. All descriptor arrays and transmit statuses need to be aligned on 4 byte boundaries; receive status arrays need to be aligned on 8 byte boundaries. The number of descriptors in the descriptor arrays needs to be written to the TxDescriptorNumber/RxDescriptorNumber registers using a -1 encoding i.e.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet After writing the descriptor the descriptor needs to be handed over to the hardware by incrementing (and possibly wrapping) the TxProduceIndex register. If the transmit data path is disabled, the device driver should not forget to enable the transmit data path by setting the TxEnable bit in the Command register.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet frame descriptors, and sends them out as one Ethernet frame on the Ethernet connection. When the Tx DMA manager finds a descriptor with the Last bit in the Control field set to 1, this indicates the last fragment of the frame and thus the end of the frame is found.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet The transmission can generate several types of errors: LateCollision, ExcessiveCollision, ExcessiveDefer, Underrun, and NoDescriptor. All have corresponding bits in the transmission StatusInfo word. In addition to the separate bits in the StatusInfo word, LateCollision, ExcessiveCollision, and ExcessiveDefer are ORed together into the Error bit of the Status.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet • In the case of a transmission error (LateCollision, ExcessiveCollision, or ExcessiveDefer) or a multi-fragment frame where the device driver did provide the initial fragments but did not provide the rest of the fragments (NoDescriptor) or in the case of a nonfatal overrun, the hardware will set the TxErrorInt bit of the IntStatus register.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet boundary. Since the number of descriptors matches the number of statuses the status array consists of four elements; the array is 4x1x4 bytes and aligned on a 4 byte address boundary. The device driver writes the base address of the descriptor array (0x2008 10EC) to the TxDescriptor register and the base address of the status array (0x2008 11F8) to the TxStatus register.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet After transmitting each fragment of the frame the Tx DMA will write the status of the fragment’s transmission. Statuses for all but the last fragment in the frame will be written as soon as the data in the frame has been accepted by the Tx DMA manager. The status for the last fragment in the frame will only be written after the transmission has completed on the Ethernet connection.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet Rx DMA manager reads Rx descriptor arrays When the RxEnable bit in the Command register is set, the Rx DMA manager reads the descriptors from memory at the address determined by RxDescriptor and RxProduceIndex. The Ethernet block will start reading descriptors even before actual receive data arrives on the RMII interface (descriptor prefetching).
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet If the descriptor is for the last fragment of a frame (or for the whole frame if there are no fragments), then depending on the success or failure of the frame reception, error flags (Error, NoDescriptor, Overrun, AlignmentError, RangeError, LengthError, SymbolError, or CRCError) are set in StatusInfo. The RxSize field is set to the number of bytes actually written to the fragment buffer, -1 encoded.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet receive errors cannot be reported in the receiver Status arrays which corrupts the hardware state; the errors will still be reported in the IntStatus register’s Overrun bit. The RxReset bit in the Command register should be used to soft reset the hardware. Device drivers should catch the above receive errors and take action.
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UM10360 NXP Semiconductors Status 0 Status 1 1 CONTROL 7 0x20081418 0x200810F0 0x20081411 FRAGMENT 0 BUFFER(8 bytes) PACKET 0x20081409 Descriptor 0 0x200810EC RxStatus 0x200811F8 StatusInfo 7 0x200811F8 StatusHashCRC StatusInfo 7 0x20081200 StatusHashCRC Status 2 Status 3 0x2008141B 0x200810F8 1 CONTROL 7 0x20081419 PACKET 0x20081411 0x20081100 1 CONTROL 7 0x20081325 PACKET 0x20081419 StatusInfo 2 0x20081208 StatusHashCRC StatusInfo 7 0x20081210 StatusHashCRC 0x2008132C FRA
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet continuous memory space; even when a frame is distributed over multiple fragments it will typically be in a linear, continuous memory space; when the descriptors wrap at the end of the descriptor array the frame will not be in a continuous memory space.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet Each four pairs of bits transferred on the RMII interface are transferred as a byte on the data write interface after being delayed by 128 or 136 cycles for filtering by the receive filter and buffer modules. The Ethernet block removes preamble, frame start delimiter, and CRC from the data and checks the CRC. To limit the buffer NoDescriptor error probability, three descriptors are buffered.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet 10.17.7 Duplex modes The Ethernet block can operate in full duplex and half duplex mode. Half or full duplex mode needs to be configured by the device driver software during initialization. For a full duplex connection the FullDuplex bit of the Command register needs to be set to 1 and the FULL-DUPLEX bit of the MAC2 configuration register needs to be set to 1; for half duplex the same bits need to be set to 0. 10.17.8 IEE 802.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet If the MAC is operating in full-duplex mode, then setting the TxFlowControl bit of the Command register will start a pause frame transmission. The value inserted into the pause-timer value field of transmitted pause frames is programmed via the PauseTimer[15:0] bits in the FlowControlCounter register.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet device driver PauseTimer register MirrorCounter TxFlowCtl writes RMII transmit clear TxFlowCtl normal transmission pause control frame transmission pause control frame transmission normal transimisson pause control frame transmission MirrorCounter (1/515 bit slots) RMII receive 0 pause in effect normal receive 50 100 150 200 250 300 normal receive 350 400 450 500 Fig 23.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet 10.17.10 Receive filtering Features of receive filtering The Ethernet MAC has several receive packet filtering functions that can be configured from the software driver: • Perfect address filter: allows packets with a perfectly matching station address to be identified and passed to the software driver. • Hash table filter: allows imperfect filtering of packets based on the station address.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet packet AcceptUnicastEn AcceptMulticastEn IMPERFECT HASH FILTER AcceptUnicastHashEn StationAddress AcceptMulticastHashEn AcceptPerfectEn PERFECT ADDRESS FILTER PAMatch PAReady HFReady H FMatc h HashFilter CRC OK? FMatch RxFilterWoL RxFilterEnWoL RxAbort FReady Fig 24.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet • Hash function: – The standard Ethernet cyclic redundancy check (CRC) function is calculated from the 6 byte destination address in the Ethernet frame (this CRC is calculated anyway as part of calculating the CRC of the whole frame), then bits [28:23] out of the 32-bit CRC result are taken to form the hash.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet The Ethernet block supports power management with remote wake-up over LAN. The host system can be powered down, even including part of the Ethernet block itself, while the Ethernet block continues to listen to packets on the LAN. Appropriately formed packets can be received and recognized by the Ethernet block and used to trigger the host system to wake up from its power-down state. Wake-up of the system takes effect through an interrupt.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet Magic Packet filtering is enabled by setting the MagicPacketEnWoL bit of the RxFilterCtrl register. Note that when doing Magic Packet WoL, the RxFilterEnWoL bit in the RxFilterCtrl register should be 0. Setting the RxFilterEnWoL bit to 1 would accept all packets for a matching address, not just the Magic Packets i.e. WoL using Magic Packets is more strict.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet ACTIVE RxStatus = 1 xxxxxxxxxxxxxxxxxx RxEnable = 0 and not busy receiving OR RxProduceIndex = RxConsumeIndex - 1 RxEnable = 1 INACTIVE RxStatus = 0 reset Fig 25. Receive Active/Inactive state machine After a reset, the state machine is in the INACTIVE state. As soon as the RxEnable bit is set in the Command register, the state machine transitions to the ACTIVE state.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet ACTIVE TxStatus = 1 xxxxxxxxxxxxxxxxxxxxxx TxEnable = 1 AND TxProduceIndex <> TxConsumeIndex TxEnable = 0 and not busy transmitting OR TxProduceIndex = TxConsumeIndex INACTIVE TxStatus = 0 reset Fig 26. Transmit Active/Inactive state machine After reset, the state machine is in the INACTIVE state.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet If EPADEN is 1, then small frames will be padded and a CRC will always be added to the padded frames.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet 10.17.18 Reset The Ethernet block has a hard reset input which is connected to the chip reset, as well as several soft resets which can be activated by setting the appropriate bit(s) in registers. All registers in the Ethernet block have a value of 0 after a hard reset, unless otherwise specified. Hard reset After a hard reset, all registers will be set to their default value.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet • RegReset: Resets all of the data paths and registers in the host registers module, excluding the registers in the MAC. A soft reset of the registers will also abort all AHB transactions of the transmit and receive data path. The reset bit will be cleared autonomously by the Ethernet block. To do a full soft reset of the Ethernet block, device driver software must: • • • • Set the ‘SOFT RESET’ bit in the MAC1 register to 1.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet 10.18 AHB bandwidth The Ethernet block is connected to an AHB bus which must carry all of the data and control information associated with all Ethernet traffic in addition to the CPU accesses required to operate the Ethernet block and deal with message contents. 10.18.1 DMA access Assumptions By making some assumptions, the bandwidth needed for each type of AHB transfer can be calculated and added in order to find the overall bandwidth requirement.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet • Rx status write: – Receive status occupies 2 words (8 bytes) of memory and is written once for each use of a descriptor. – Two word write happens once every 64 bytes (16 words) of received data. – This gives 1/8 of the data rate, which = 1.5625 Mbps. • Tx data read: – Data transmitted in an Ethernet frame, the size is variable. – Basic Ethernet rate = 12.5 Mbps. • Rx data write: – Data to be received in an Ethernet frame, the size is variable.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet for Ethernet traffic during simultaneous transmit and receive operations. This shows that it is not necessary to use the maximum CPU frequency for the Ethernet to work with plenty of bandwidth headroom. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 August 2010 © NXP B.V. 2010. All rights reserved.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet 10.19 CRC calculation The calculation is used for several purposes: • Generation the FCS at the end of the Ethernet frame. • Generation of the hash table index for the hash table filtering. • Generation of the destination and source address hash CRCs. The C pseudocode function below calculates the CRC on a frame taking the frame (without FCS) and the number of bytes in the frame as arguments. The function returns the CRC as a 32-bit integer.
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UM10360 NXP Semiconductors Chapter 10: LPC17xx Ethernet For hash filtering, this function is passed a pointer to the destination address part of the frame and the CRC is only calculated on the 6 address bytes. The hash filter uses bits [28:23] for indexing the 64-bits { HashFilterH, HashFilterL } vector. If the corresponding bit is set the packet is passed, otherwise it is rejected by the hash filter.
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UM10360 Chapter 11: LPC17xx USB device controller Rev. 2 — 19 August 2010 User manual 11.1 How to read this chapter This chapter describes the USB controller which is present on all LPC17xx devices except the LPC1767. On some LPC17xx family devices, the USB controller can also be configured for Host or OTG operation. 11.2 Basic configuration The USB controller is configured using the following registers: 1. Power: In the PCONP register (Table 46), set bit PCUSB.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Table 184.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Table 185.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller VBUS BUS MASTER INTERFACE DMA ENGINE USB_CONNECT EP_RAM ACCESS CONTROL REGISTER INTERFACE SERIAL INTERFACE ENGINE USB ATX AHB BUS DMA interface (AHB master) USB_D+ USB_D- USB_UP_LED register interface (AHB slave) EP_RAM (4K) USB DEVICE BLOCK Fig 27. USB device controller block diagram 11.6.1 Analog transceiver The USB Device Controller has a built-in analog transceiver (ATX).
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller 11.6.5 DMA engine and bus master interface When enabled for an endpoint, the DMA Engine transfers data between RAM on the AHB bus and the endpoint’s buffer in EP_RAM. A single DMA channel is shared between all endpoints. When transferring data, the DMA Engine functions as a master on the AHB bus through the bus master interface. 11.6.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Once data has been received or sent, the endpoint buffer can be read or written. How this is accomplished depends on the endpoint’s type and operating mode. The two operating modes for each endpoint are Slave (CPU-controlled) mode, and DMA mode. In Slave mode, the CPU transfers data between RAM and the endpoint buffer using the Register Interface. See Section 11.14 “Slave mode operation” for a detailed description of this mode.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Table 187. USB device controller clock sources Clock source Description AHB master clock Clock for the AHB master bus interface and DMA AHB slave clock Clock for the AHB slave interface usbclk 48 MHz clock from the dedicated USB PLL (PLL1) or the Main PLL (PLL0), used to recover the 12 MHz clock from the USB bus 11.9.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller 11.9.4 Remote wake-up The USB device controller supports software initiated remote wake-up. Remote wake-up involves resume signaling on the USB bus initiated from the device. This is done by clearing the SUS bit in the SIE Set Device Status register. Before writing into the register, all the clocks to the device controller have to be enabled using the USBClkCtrl register. 11.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Table 188.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Table 189. USBClkCtrl register (USBClkCtrl - address 0x5000 CFF4) bit description Bit Symbol Description Reset value 3 - Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 4 AHB_CLK_EN AHB clock enable 0 31:5 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 11.10.1.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Table 191. USB Interrupt Status register (USBIntSt - address 0x5000 C1C0) bit description Bit Symbol Description Reset value 8 USB_NEED_CLK USB need clock indicator. This bit is set to 1 when USB activity or a change 1 of state on the USB data pins is detected, and it indicates that a PLL supplied clock of 48 MHz is needed.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Table 193. USB Device Interrupt Status register (USBDevIntSt - address 0x5000 C200) bit description Bit Symbol Description 8 EP_RLZED Endpoints realized. Set when Realize Endpoint register (USBReEp) or MaxPacketSize 0 register (USBMaxPSize) is updated and the corresponding operation is completed. 9 ERR_INT Error Interrupt. Any bus error interrupt from the USB device. Refer to Section 11.12.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Bit Symbol Bit Symbol Bit Symbol 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - ERR_INT EP_RLZED 7 6 5 4 3 2 1 0 TxENDPKT Rx ENDPKT CDFULL CCEMPTY DEV_STAT EP_SLOW EP_FAST FRAME Table 197.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Table 200. USB Device Interrupt Priority register (USBDevIntPri - address 0x5000 C22C) bit description Bit Symbol Value Description Reset value 0 FRAME 0 FRAME interrupt is routed to USB_INT_REQ_LP. 0 1 FRAME interrupt is routed to USB_INT_REQ_HP. 0 EP_FAST interrupt is routed to USB_INT_REQ_LP. 1 EP_FAST 31:2 - 1 0 EP_FAST interrupt is routed to USB_INT_REQ_HP.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Table 202. USB Endpoint Interrupt Status register (USBEpIntSt - address 0x5000 C230) bit description Bit Symbol Description Reset value 6 EP3RX Endpoint 3, Isochronous endpoint. NA 7 EP3TX Endpoint 3, Isochronous endpoint. NA 8 EP4RX Endpoint 4, Data Received Interrupt bit. 0 9 EP4TX Endpoint 4, Data Transmitted Interrupt bit or sent a NAK. 0 10 EP5RX Endpoint 5, Data Received Interrupt bit.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Bit Symbol 7 6 5 4 3 2 1 0 EP3TX EP3RX EP2TX EP2RX EP1TX EP1RX EP0TX EP0RX Table 204. USB Endpoint Interrupt Enable register (USBEpIntEn - address 0x5000 C234) bit description Bit Symbol Value 31:0 See USBEpIntEn bit 0 allocation table above Description Reset value The corresponding bit in USBDMARSt is set when an interrupt occurs 0 for this endpoint.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller 11.10.3.4 USB Endpoint Interrupt Set register (USBEpIntSet - 0x5000 C23C) Writing a one to a bit in this register sets the corresponding bit in USBEpIntSt. Writing zero has no effect. Each endpoint has its own bit in this register. USBEpIntSet is a write-only register. Table 207.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Table 210. USB Endpoint Interrupt Priority register (USBEpIntPri - address 0x5000 C240) bit description Bit Symbol Value Description Reset value 31:0 See USBEpIntPri bit allocation table above 0 The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 0 1 The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt 11.10.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Table 211.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller The device will not respond to any transactions to unrealized endpoints. The SIE Configure Device command will only cause realized and enabled endpoints to respond to transactions. For details see Table 243. 11.10.4.3 USB Endpoint Index register (USBEpIn - 0x5000 C248) Each endpoint has a register carrying the MaxPacketSize value for that endpoint. This is in fact a register array.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller 11.10.5.1 USB Receive Data register (USBRxData - 0x5000 C218) For an OUT transaction, the CPU reads the endpoint buffer data from this register. Before reading this register, the RD_EN bit and LOG_ENDPOINT field of the USBCtrl register should be set appropriately. On reading this register, data from the selected endpoint buffer is fetched.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller 11.10.5.4 USB Transmit Packet Length register (USBTxPLen - 0x5000 C224) This register contains the number of bytes transferred from the CPU to the selected endpoint buffer. Before writing data to USBTxData, software should first write the packet length (≤ MaxPacketSize) to this register. After each write to USBTxData, hardware decrements USBTxPLen by 4.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller 11.10.6.1 USB Command Code register (USBCmdCode - 0x5000 C210) This register is used for sending the command and write data to the SIE. The commands written here are propagated to the SIE and executed there. After executing the command, the register is empty, and the CCEMPTY bit of USBDevIntSt register is set. See Section 11.12 for details. USBCmdCode is a write-only register. Table 220.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Bit Symbol Bit Symbol Bit Symbol 23 22 21 20 19 18 17 16 EP23 EP22 EP21 EP20 EP19 EP18 EP17 EP16 15 14 13 12 11 10 9 8 EP15 EP14 EP13 EP12 EP11 EP10 EP9 EP8 7 6 5 4 3 2 1 0 EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP0 Table 223.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller This register allows software to raise a DMA request. This can be useful when switching from Slave to DMA mode of operation for an endpoint: if a packet to be processed in DMA mode arrives before the corresponding bit of USBEpIntEn is cleared, the DMA request is not raised by hardware. Software can then use this register to manually start the DMA transfer.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller 11.10.7.6 USB EP DMA Enable register (USBEpDMAEn - 0x5000 C288) Writing one to a bit to this register will enable the DMA operation for the corresponding endpoint. Writing zero has no effect.The DMA cannot be enabled for control endpoints EP0 and EP1. USBEpDMAEn is a write-only register. Table 228.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Table 230. USB DMA Interrupt Status register (USBDMAIntSt - address 0x5000 C290) bit description Bit Symbol 2 ERR Value 0 31:3 - Description Reset value System Error Interrupt bit. 0 All bits in the USBSysErrIntSt register are 0. 1 At least one bit in the USBSysErrIntSt is set. - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 11.10.7.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Table 233. USB End of Transfer Interrupt Clear register (USBEoTIntClr - address 0x5000 C2A4) bit description Bit Symbol 31:0 EPxx Value Description Reset value Clear endpoint xx (2 ≤ xx ≤ 31) End of Transfer Interrupt request. 0 0 No effect. 1 Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. 11.10.7.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Table 237. USB New DD Request Interrupt Set register (USBNDDRIntSet - address 0x5000 C2B4) bit description Bit Symbol 31:0 EPxx Value Description Reset value Set endpoint xx (2 ≤ xx ≤ 31) new DD interrupt request. 0 0 No effect. 1 Set the EPxx new DD interrupt request in the USBNDDRIntSt register. 11.10.7.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller The interrupt handling is different for Slave and DMA mode. Slave mode If an interrupt event occurs on an endpoint and the endpoint interrupt is enabled in the USBEpIntEn register, the corresponding status bit in the USBEpIntSt is set. For non-isochronous endpoints, all endpoint interrupt events are divided into two types by the corresponding USBEpIntPri[n] registers: fast endpoint interrupt events and slow endpoint interrupt events.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller interrupt event on EPn Slave mode USBEpIntSt from other Endpoints . . . . FRAME EP_FAST EP_SLOW . . . . n USBEpIntEn[n] USBDevIntSt USBDevIntPri[0] . . . . . . . . . USBEpIntPri[n] .. . . . . . USBDevIntPri[1] ERR_INT USBIntSt USBDMARSt USB_INT_REQ_HP USB_INT_REQ_LP USB_INT_REQ_DMA to NVIC to DMA engine n EN_USB_INTS USBEoTIntST DMA Mode 0 . . . . 31 USBNDDRIntSt 0 USBDMAIntSt . . . .
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller 11.12 Serial interface engine command description The functions and registers of the Serial Interface Engine (SIE) are accessed using commands, which consist of a command code followed by optional data bytes (read or write action). The USBCmdCode (Table 220) and USBCmdData (Table 221) registers are used for these accesses. A complete access consists of two phases: 1.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Table 241.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Table 243. Configure Device command bit description Bit Symbol Description Reset value 0 CONF_DEVICE Device is configured. All enabled non-control endpoints will respond. This bit is cleared by hardware when a bus reset occurs. When set, the UP_LED signal is driven LOW if the device is not in the suspended state (SUS=0). 7:1 - Reserved, user software should not write ones to reserved bits.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller • In case no SOF was received by the device at the beginning of a frame, the frame number returned is that of the last successfully received SOF. • In case the SOF frame number contained a CRC error, the frame number returned will be the corrupted frame number as received by the device. 11.12.5 Read Test Register (Command: 0xFD, Data: read 2 bytes) The test register is 16 bits wide.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Table 245. Set Device Status command bit description Bit Symbol 4 RST Value Description Reset value Bus Reset bit. On a bus reset, the device will automatically go to the default state. In the default state: 0 • • • • • • • • Device is unconfigured. Will respond to address 0. Control endpoint will be in the Stalled state. All endpoints are unrealized except control endpoints EP0 and EP1.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Table 246. Get Error Code command bit description Bit Symbol 3:0 EC 4 EA 7:5 - Value Description Reset value Error Code. 0x0 0000 No Error. 0001 PID Encoding Error. 0010 Unknown PID. 0011 Unexpected Packet - any packet sequence violation from the specification. 0100 Error in Token CRC. 0101 Error in Data CRC. 0110 Time Out Error. 0111 Babble. 1000 Error in End of Packet. 1001 Sent/Received NAK.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Table 248. Select Endpoint command bit description Bit Symbol 0 FE 1 2 3 4 5 6 7 Value Description Reset value Full/Empty. This bit indicates the full or empty status of the endpoint buffer(s). For IN endpoints, the FE bit gives the ANDed result of the B_1_FULL and B_2_FULL bits. For OUT endpoints, the FE bit gives ORed result of the B_1_FULL and B_2_FULL bits.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Remark: This command may be invoked by using the USBCmdCode and USBCmdData registers, or by setting the corresponding bit in USBEpIntClr. For ease of use, using the USBEpIntClr register is recommended. 11.12.12 Set Endpoint Status (Command: 0x40 - 0x55, Data: write 1 byte (optional)) The Set Endpoint Status command sets status bits 7:5 and 0 of the endpoint.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller the SETUP data. If it is set then it should discard the previously read data, clear the PO bit by issuing a Select Endpoint/Clear Interrupt command, read the new SETUP data and again check the status of the PO bit. See Section 11.14 “Slave mode operation” for a description of when this command is used. Table 250. Clear Buffer command bit description Bit Symbol Value Description Reset value 0 PO 0 7:1 - Packet over-written bit.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller 6. Set USBEpIn and USBMaxPSize registers for EP0 and EP1, and wait until the EP_RLZED bit in USBDevIntSt is set so that EP0 and EP1 are realized. 7. Enable endpoint interrupts (Slave mode): – Clear all endpoint interrupts using USBEpIntClr. – Clear any device interrupts using USBDevIntClr. – Enable Slave mode for the desired endpoints by setting the corresponding bits in USBEpIntEn.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller All non-isochronous OUT endpoints generate an endpoint interrupt when they receive a packet without an error. All non-isochronous IN endpoints generate an interrupt when a packet is successfully transmitted, or when a NAK handshake is sent on the bus and the interrupt on NAK feature is enabled. For Isochronous endpoints, transfer of data is done when the FRAME interrupt (in USBDevIntSt) occurs. 11.14.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Section 11.15.4 “The DMA descriptor”. The last three sections describe DMA operation: Section 11.15.5 “Non-isochronous endpoint operation”, Section 11.15.6 “Isochronous endpoint operation”, and Section 11.15.7 “Auto Length Transfer Extraction (ATLE) mode operation”. 11.15.1 Transfer terminology Within this section three types of transfers are mentioned: 1. USB transfers – transfer of data over the USB bus. The USB 2.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller UDCA 0 NULL NULL 1 NULL Next_DD_pointer Next_DD_pointer Next_DD_pointer DD-EP2-a DD-EP2-b DD-EP2-c 2 DDP-EP2 NULL UDCA HEAD REGISTER NULL Next_DD_pointer Next_DD_pointer DD-EP16-a DD-EP16-b 16 DDP-EP16 31 DDP-EP31 Fig 30. UDCA Head register and DMA Descriptors 11.15.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller • • • • • The length of the DMA buffer The start address of the next DMA descriptor Control information Count information (number of bytes transferred) Status information Table 251 lists the DMA descriptor fields. Table 251.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller 11.15.4.2 DMA_mode Specifies the DMA mode of operation. Two modes have been defined: Normal and Automatic Transfer Length Extraction (ATLE) mode. In normal mode, software initializes the DMA_buffer_length for OUT endpoints. In ATLE mode, the DMA_buffer_length is extracted from the incoming data. See Section 11.15.7 “Auto Length Transfer Extraction (ATLE) mode operation” on page 263 for more details. 11.15.4.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller • DataUnderrun - Before reaching the end of the DMA buffer, the USB transfer is terminated because a short packet is received. The DD_retired bit is also set. • DataOverrun - The end of the DMA buffer is reached in the middle of a packet transfer. This is an error situation. The DD_retired bit is set. The present DMA count field is equal to the value of DMA_buffer_length.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller 11.15.5 Non-isochronous endpoint operation 11.15.5.1 Setting up DMA transfers Software prepares the DMA Descriptors (DDs) for those physical endpoints to be enabled for DMA transfer. These DDs are present in on-chip RAM. The start address of the first DD is programmed into the DMA Description pointer (DDP) location for the corresponding endpoint in the UDCA.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller The DMA_PROCEED flag is cleared after the required number of bytes specified in the DMA_buffer_length field is transferred. It is also cleared when the software writes into the USBEpDMADis register. The ability to clear the DMA_PROCEED flag allows software to to force the DD to be re-fetched for the next packet transfer.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller For isochronous endpoints, the DMA_buffer_length and Present_DMA_count fields are in frames rather than bytes. 11.15.6.2 Finding the DMA Descriptor Finding the descriptors is done in the same way as that for a non-isochronous endpoint. A DMA request will be placed for DMA-enabled isochronous endpoints on every FRAME interrupt.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller Next_DD_Pointer W0 NULL DMA_buffer_length W1 Max_packet_size 0x000A Isochronous_endpoint 0x0 Next_DD_Valid 1 DMA_mode 0 0 DMA_buffer_start_addr W2 0x80000000 Present_DMA_Count ATLE settings Packet_Valid DD_Status 0x0 NA NA 0x0 DD_Retired W3 0 Isocronous_packetsize_memory_address W4 0x60000000 after 4 packets W0 0x0 W1 0x000A0010 FULL 0x80000035 W2 W3 0x4 - - 0x1 0 frame_ number Packet_Valid Packet_Lengt
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller data to be sent data in packets data to be stored in by host driver as seen on USB RAM by DMA engine 160 bytes 64 bytes DMA_buffer_start_addr of DD1 160 bytes 64 bytes 32 bytes 32 bytes 100 bytes 100 bytes 64 bytes DMA_buffer_start_addr of DD2 4 bytes Fig 32.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller In ATLE mode, the last buffer length to be transferred always ends with a short or empty packet indicating the end of the USB transfer. If the concatenated transfer lengths are such that the USB transfer ends on a MaxPacketSize packet boundary, the (NDIS) host will send an empty packet to mark the end of the USB transfer.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller 11.15.7.4 Ending the packet transfer The DMA engine proceeds with the transfer until the number of bytes specified in the field DMA_buffer_length is transferred to or from on-chip RAM. Then the EOT interrupt will be generated. If this happens in the middle of the packet, the linked DD will get loaded and the remaining part of the packet gets transferred to or from the address pointed by the new DD.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller 5. Software sends the SIE Select Endpoint command to read the Select Endpoint Register and test the FE bit. Software finds that the active buffer (B_2) has data (FE=1). Software clears the endpoint interrupt and begins reading the contents of B_2. 6. The host re-sends the third packet which device hardware places in B_1. An endpoint interrupt is generated. 7.
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UM10360 NXP Semiconductors Chapter 11: LPC17xx USB device controller 11. Both B_1 and B_2 are empty, and the active buffer is B_2. The next packet written by software will go into B_2. In DMA mode, switching of the active buffer is handled automatically in hardware. For Bulk IN endpoints, proactively filling an endpoint buffer to take advantage of the double buffering can be accomplished by manually starting a packet transfer using the USBDMARSet register. 11.16.
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UM10360 Chapter 12: LPC17xx USB Host controller Rev. 2 — 19 August 2010 User manual 12.1 How to read this chapter The USB host controller is available on the LPC1768, LPC1766, LPC1765, LPC1758, LPC1756, and LPC1754. On these devices, the USB controller can be configured for device, Host, or OTG operation. 12.2 Basic configuration The USB controller is configured using the following registers: 1. Power: In the PCONP register (Table 46), set bit PCUSB.
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UM10360 NXP Semiconductors Chapter 12: LPC17xx USB Host controller Table 252. USB (OHCI) related acronyms and abbreviations used in this chapter Acronym/abbreviation Description LS Low Speed OHCI Open Host Controller Interface USB Universal Serial Bus 12.3.1 Features • OHCI compliant. • OpenHCI specifies the operation and interface of the USB Host Controller and SW Driver – USBOperational: Process Lists and generate SOF Tokens. – USBReset: Forces reset signaling on the bus, SOF disabled.
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UM10360 NXP Semiconductors Chapter 12: LPC17xx USB Host controller 12.4.1 Pin description Table 253. USB Host port pins Pin name Direction Description Type USB_D+ I/O Positive differential data USB Connector USB_D− I/O Negative differential data USB Connector USB_UP_LED O GoodLink LED control signal Control USB_PPWR O Port power enable Host power switch USB_PWRD I Port power status Host power switch USB_OVRCR I Over-current status Host power switch 12.4.1.
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UM10360 NXP Semiconductors Chapter 12: LPC17xx USB Host controller Table 254. USB Host register address definitions …continued Name Address R/W[1] Function Reset value HcControlHeadED 0x5000 C020 R/W Contains the physical address of the first endpoint descriptor of the control list.
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UM10360 Chapter 13: LPC17xx USB OTG Rev. 2 — 19 August 2010 User manual 13.1 How to read this chapter The USB OTG controller is available in the LPC1768, LPC1766, LPC1765, LPC1758, LPC1756, and LPC1754. On these devices, the USB controller can be configured for device, Host, or OTG operation. 13.2 Basic configuration The USB controller is configured using the following registers: 1. Power: In the PCONP register (Table 46), set bit PCUSB. Remark: On reset, the USB block is disabled (PCUSB = 0). 2.
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UM10360 NXP Semiconductors Chapter 13: LPC17xx USB OTG 13.5 Architecture The architecture of the USB OTG controller is shown below in the block diagram. The host, device, OTG, and I2C controllers can be programmed through the register interface. The OTG controller enables dynamic switching between host and device roles through the HNP protocol. One port may be connected to an external OTG transceiver to support an OTG connection.
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UM10360 NXP Semiconductors Chapter 13: LPC17xx USB OTG 13.7 Pin configuration The OTG controller has one USB port. Table 255.
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UM10360 NXP Semiconductors Chapter 13: LPC17xx USB OTG 13.7.2 Connecting USB as a host The USB port is connected as host using an embedded USB transceiver. There is no OTG functionality on the port. VDD USB_UP_LED VSS USB_D+ 33 Ω D+ USB_D− 33 Ω D− LPC176x 15 kΩ USB-A connector 15 kΩ VDD VBUS USB_PWRD USB_OVRCR USB_PPWR FLAGA ENA 5V IN LM3526-L OUTA graphicID Fig 36. USB host port configuration 13.7.3 Connecting USB as device The USB port is connected as device.
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UM10360 NXP Semiconductors Chapter 13: LPC17xx USB OTG 13.8 Register description The OTG and I2C registers are summarized in the following table. The Device and Host registers are explained in Table 254 and Table 188 in the USB Device Controller and USB Host (OHCI) Controller chapters. All registers are 32 bits wide and aligned to word address boundaries. Table 256.
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UM10360 NXP Semiconductors Chapter 13: LPC17xx USB OTG Table 257. USB Interrupt Status register - (USBIntSt - address 0x5000 C1C0) bit description Bit Symbol Description Reset Value 4 USB_ATX_INT External ATX interrupt line status. This bit is read-only. 0 5 USB_OTG_INT OTG interrupt line status. This bit is read-only. 0 6 USB_I2C_INT I2C module interrupt line status. This bit is read-only. 0 7 - Reserved, user software should not write ones to reserved bits.
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UM10360 NXP Semiconductors Chapter 13: LPC17xx USB OTG 13.8.5 OTG Interrupt Clear Register (OTGIntClr - 0x5000 C10C) Writing a one to a bit in this register will clear the corresponding bit in the OTGIntSt register. Writing a zero has no effect. The bit allocation of OTGIntClr is the same as in OTGIntSt. 13.8.
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UM10360 NXP Semiconductors Chapter 13: LPC17xx USB OTG Table 259. OTG Status Control register (OTGStCtrl - address 0x5000 C110) bit description Bit Symbol Description Reset Value 10 PU_REMOVED When the B-device changes its role from peripheral to host, software sets this bit when it removes the D+ pull-up, see Section 13.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set. 0 15:11 - Reserved, user software should not write ones to reserved bits.
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UM10360 NXP Semiconductors Chapter 13: LPC17xx USB OTG Table 261. OTG clock control register (OTG_clock_control - address 0x5000 CFF4) bit description Bit Symbol 4 AHB_CLK_EN 31:5 Value - Description Reset Value AHB master clock enable 0 0 Disable the AHB clock. 1 Enable the AHB clock. NA Reserved, user software should not write ones NA to reserved bits. The value read from a reserved bit is not defined. 13.8.
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UM10360 NXP Semiconductors Chapter 13: LPC17xx USB OTG Table 263. I2C Receive register (I2C_RX - address 0x5000 C300) bit description Bit Symbol Description Reset Value 7:0 RX Data Receive data. - 13.8.11 I2C Transmit Register (I2C_TX - 0x5000 C300) This register is the top byte of the transmit FIFO. The transmit FIFO is 4 bytes deep. The Tx FIFO is flushed by a hard reset, soft reset (I2C_CTL bit 7) or if an arbitration failure occurs (I2C_STS bit 3). Data writes to a full FIFO are ignored.
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UM10360 NXP Semiconductors Chapter 13: LPC17xx USB OTG Table 265. I2C status register (I2C_STS - address 0x5000 C304) bit description Bit Symbol Value Description 2 NAI 3 4 No Acknowledge Interrupt. After every byte of data is sent, the 0 transmitter expects an acknowledge from the receiver. This bit is set if the acknowledge is not received. It is cleared when a byte is written to the master TX FIFO. 0 Last transmission received an acknowledge.
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UM10360 NXP Semiconductors Chapter 13: LPC17xx USB OTG Table 265. I2C status register (I2C_STS - address 0x5000 C304) bit description Bit Symbol Value Description Reset Value 11 TFE 1 Transmit FIFO Empty. TFE is set when the TX FIFO is empty and is cleared when the TX FIFO contains valid data. 31:12 - 0 TX FIFO contains valid data. 1 TX FIFO is empty NA Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 13.8.
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UM10360 NXP Semiconductors Chapter 13: LPC17xx USB OTG Table 266. I2C Control register (I2C_CTL - address 0x5000 C308) bit description Bit Symbol 6 RFDAIE 7 8 Value Description Receive Data Available Interrupt Enable. This enables the DAI interrupt to indicate that data is available in the receive FIFO (i.e. not empty). 0 Disable the DAI. 1 Enable the DAI. TFFIE 0 Transmit FIFO Not Full Interrupt Enable.
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UM10360 NXP Semiconductors Chapter 13: LPC17xx USB OTG I2C related interrupts are set in the I2C_STS register and routed, if enabled by I2C_CTL, to the USB_I2C_INT bit. For more details on the interrupts created by device controller, see the USB device chapter. For interrupts created by the host controllers, see the OHCI specification. The EN_USB_INTS bit in the USBIntSt register enables the routing of any of the USB related interrupts to the NVIC controller (see Figure 38).
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UM10360 NXP Semiconductors Chapter 13: LPC17xx USB OTG The OTG software stack is responsible for implementing the HNP state machines as described in the On-The-Go Supplement to the USB 2.0 Specification. The OTG controller hardware provides support for some of the state transitions in the HNP state machines as described in the following subsections.
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UM10360 NXP Semiconductors Chapter 13: LPC17xx USB OTG idle B_HNP_TRACK = 0 no B_HNP_TRACK = 1 ? set HNP_FAILURE, clear B_HNP_TRACK, clear PU_REMOVED no bus suspended ? no disconnect device controller from U1 set REMOVE_PU yes PU_REMOVED set? PU_REMOVED set? reconnect port U1 to the device controller bus reset/resume detected? yes no reconnect port U1 to the device controller wait 25 μs for bus to settle yes yes bus reset/resume detected? connect from A-device detected? no set HNP_SUCC
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UM10360 NXP Semiconductors Chapter 13: LPC17xx USB OTG b_peripheral when host sends SET_FEATURE with b_hnp_enable, set B_HNP_TRACK no REMOVE_PU set? yes remove D+ pull-up, set PU_REMOVED go to go to b_wait_acon b_peripheral HNP_FAILURE set? yes add D+ pull-up no no HNP_SUCCESS set? yes go to b_host Fig 41.
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UM10360 NXP Semiconductors Chapter 13: LPC17xx USB OTG /* Wait for TDI to be set */ while (!(OTG_I2C_STS & TDI)); /* Clear TDI */ OTG_I2C_STS = TDI; Add D+ pull-up /* Add D+ pull-up through ISP1302 */ OTG_I2C_TX = 0x15A; // Send ISP1302 address, R/W=0 OTG_I2C_TX = 0x006; // Send OTG Control (Set) register address OTG_I2C_TX = 0x201; // Set DP_PULLUP bit, send STOP condition /* Wait for TDI to be set */ while (!(OTG_I2C_STS & TDI)); /* Clear TDI */ OTG_I2C_STS = TDI; 13.9.
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UM10360 NXP Semiconductors Chapter 13: LPC17xx USB OTG idle A_HNP_TRACK = 0 no A_HNP_TRACK = 1 ? set HNP_FAILURE, clear A_HNP_TRACK disconnect host controller from U1 no no bus suspended ? resume detected ? yes yes connnect host controller back to U1 yes yes bus reset detected? resume detected? no no no OTG timer expired? (TMR =1 ) yes clear A_HNP_TRACK set HNP_SUCCESS connect device to U1 by clearing PORT_FUNC[0] Fig 42.
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UM10360 NXP Semiconductors Chapter 13: LPC17xx USB OTG a_host when host sends SET_FEATURE with a_hnp_enable, set A_HNP_TRACK set BDIS_ACON_EN in external OTG transceiver load and enable OTG timer suspend host on port 1 go to a_suspend no no no TMR set? HNP_SUCCESS set? yes HNP_FAILURE set? yes yes clear BDIS_ACON_EN bit in external OTG transceiver discharge VBUS stop OTG timer stop the OTG timer go to a_peripheral clear BDIS_ACON_EN bit in external OTG transceiver go to go to a_wait_vfal
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UM10360 NXP Semiconductors Chapter 13: LPC17xx USB OTG /* Set BDIS_ACON_EN OTG_I2C_TX = 0x15A; OTG_I2C_TX = 0x004; OTG_I2C_TX = 0x210; in // // // ISP1302 */ Send ISP1302 address, R/W=0 Send Mode Control 1 (Set) register address Set BDIS_ACON_EN bit, send STOP condition /* Wait for TDI to be set */ while (!(OTG_I2C_STS & TDI)); /* Clear TDI */ OTG_I2C_STS = TDI; Clear BDIS_ACON_EN in external OTG transceiver /* Set BDIS_ACON_EN OTG_I2C_TX = 0x15A; OTG_I2C_TX = 0x005; OTG_I2C_TX = 0x210; in // // //
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UM10360 NXP Semiconductors Chapter 13: LPC17xx USB OTG Load and enable OTG timer /* The following assumes that the OTG timer has previously been */ /* configured for a time scale of 1 ms (TMR_SCALE = “10”) /* and monoshot mode (TMR_MODE = 0) */ */ /* Load the timeout value to implement the a_aidl_bdis_tmr timer */ /* the minimum value is 200 ms */ OTG_TIMER = 200; /* Enable the timer */ OTG_STAT_CTRL |= TMR_EN; Stop OTG timer /* Disable the timer – causes TMR_CNT to be reset to 0 */ OTG_STAT_CTRL &= ~T
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UM10360 NXP Semiconductors Chapter 13: LPC17xx USB OTG ahb_slave_clk cclk PCUSB REGISTER INTERFACE ahb_master_clk CLOCK SWITCH EN AHB_CLK_ON ahb_need_clk AHB_CLK_EN USB CLOCK DIVIDER usbclk (48 MHz) CLOCK SWITCH EN DEV_CLK_ON DEVICE CONTROLLER dev_dma_need_clk dev_need_clk DEV_CLK_EN CLOCK SWITCH EN host_dma_need_clk HOST_CLK_ON HOST CONTROLLER host_need_clk HOST_CLK_EN CLOCK SWITCH EN OTG_CLK_ON OTG CONTROLLER USB_NEED_CLK OTG_CLK_EN CLOCK SWITCH EN I2C_CLK_ON I2C CONTROLLER I2C_
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UM10360 NXP Semiconductors Chapter 13: LPC17xx USB OTG The dev_dma_need_clk signal is asserted on any Device controller DMA access to memory. Once asserted, it remains active for 2 ms (2 frames), to help assure that DMA throughput is not affected by any latency associated with re-enabling ahb_master_clk. 2 ms after the last DMA access, dev_dma_need_clk is de-asserted to help conserve power. This signal allows AHB_CLK_EN to be cleared during normal operation. 13.10.1.
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UM10360 NXP Semiconductors Chapter 13: LPC17xx USB OTG 4. Enable the desired USB pin functions by writing to the corresponding PINSEL registers. 5. Follow the appropriate steps in Section 11.13 “USB device controller initialization” to initialize the device controller. 6. Follow the guidelines given in the OpenHCI specification for initializing the host controller. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 August 2010 © NXP B.V. 2010.
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UM10360 Chapter 14: LPC17xx UART0/2/3 Rev. 2 — 19 August 2010 User manual 14.1 Basic configuration The UART0/2/3 peripherals are configured using the following registers: 1. Power: In the PCONP register (Table 46), set bits PCUART0/2/3. Remark: On reset, UART0 is enabled (PCUART0 = 1), and UART2/3 are disabled (PCUART2/3 = 0). 2. Peripheral clock: In the PCLKSEL0 register (Table 40), select PCLK_UART0; in the PCLKSEL1 register (Table 41), select PCLK_UART2/3. 3.
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UM10360 NXP Semiconductors Chapter 14: LPC17xx UART0/2/3 14.3 Pin description Table 269: UARTn Pin description Pin Type Description RXD0, RXD2, RXD3 Input Serial Input. Serial receive data. TXD0, TXD2, TXD3 Output Serial Output. Serial transmit data. 14.4 Register description Each UART contains registers as shown in Table 270. The Divisor Latch Access Bit (DLAB) is contained in UnLCR7 and enables access to the Divisor Latches.
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UM10360 NXP Semiconductors Chapter 14: LPC17xx UART0/2/3 Table 270. UART0/2/3 Register Map Generic Name Description Access Reset UARTn Register value[1] Name & Address RBR (DLAB =0) Receiver Buffer Register. Contains the next received character to be read. RO NA U0RBR - 0x4000 C000 U2RBR - 0x4009 8000 U3RBR - 0x4009 C000 THR (DLAB =0) Transmit Holding Register. The next character to be transmitted is written here.
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UM10360 NXP Semiconductors Chapter 14: LPC17xx UART0/2/3 14.4.1 UARTn Receiver Buffer Register (U0RBR - 0x4000 C000, U2RBR 0x4009 8000, U3RBR - 0x4009 C000 when DLAB = 0) The UnRBR is the top byte of the UARTn Rx FIFO. The top byte of the Rx FIFO contains the oldest character received and can be read via the bus interface. The LSB (bit 0) represents the “oldest” received data bit. If the character received is less than 8 bits, the unused MSBs are padded with zeroes.
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UM10360 NXP Semiconductors Chapter 14: LPC17xx UART0/2/3 UnLCR must be one in order to access the UARTn Divisor Latches. Details on how to select the right value for UnDLL and UnDLM can be found later in this chapter, see Section 14.4.12.
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UM10360 NXP Semiconductors Chapter 14: LPC17xx UART0/2/3 Table 275: UARTn Interrupt Enable Register (U0IER - address 0x4000 C004, U2IER - 0x4009 8004, U3IER 0x4009 C004 when DLAB = 0) bit description Bit Symbol 9 ABTOIntEn Value Description Reset Value Enables the auto-baud time-out interrupt. 31:10 - 0 Disable auto-baud time-out Interrupt. 1 Enable auto-baud time-out Interrupt. 0 Reserved, user software should not write ones to reserved bits.
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UM10360 NXP Semiconductors Chapter 14: LPC17xx UART0/2/3 The UARTn RLS interrupt (UnIIR[3:1] = 011) is the highest priority interrupt and is set whenever any one of four error conditions occur on the UARTn Rx input: overrun error (OE), parity error (PE), framing error (FE) and break interrupt (BI). The UARTn Rx error condition that set the interrupt can be observed via U0LSR[4:1]. The interrupt is cleared upon an UnLSR read.
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UM10360 NXP Semiconductors Chapter 14: LPC17xx UART0/2/3 fill up with data to eliminate many THRE interrupts from occurring at system start-up. The initialization conditions implement a one character delay minus the stop bit whenever THRE = 1 and there have not been at least two characters in the UnTHR at one time since the last THRE = 1 event. This delay is provided to give the CPU time to write data to UnTHR without a THRE interrupt to decode and service.
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UM10360 NXP Semiconductors Chapter 14: LPC17xx UART0/2/3 UART transmitter DMA In DMA mode, the transmitter DMA request is asserted on the event of the transmitter FIFO transitioning to not full. The transmitter DMA request is cleared by the DMA controller. 14.4.7 UARTn Line Control Register (U0LCR - 0x4000 C00C, U2LCR 0x4009 800C, U3LCR - 0x4009 C00C) The UnLCR determines the format of the data character that is to be transmitted or received.
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UM10360 NXP Semiconductors Chapter 14: LPC17xx UART0/2/3 Table 280: UARTn Line Status Register (U0LSR - address 0x4000 C014, U2LSR - 0x4009 8014, U3LSR - 0x4009 C014) bit description Bit Symbol 0 Receiver Data Ready (RDR) 1 2 Value Description Reset Value UnLSR0 is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty. 0 The UARTn receiver FIFO is empty. 1 The UARTn receiver FIFO is not empty.
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UM10360 NXP Semiconductors Chapter 14: LPC17xx UART0/2/3 Table 280: UARTn Line Status Register (U0LSR - address 0x4000 C014, U2LSR - 0x4009 8014, U3LSR - 0x4009 C014) bit description Bit Symbol 7 Error in RX FIFO (RXFE) 31:8 Value Description Reset Value UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO.
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UM10360 NXP Semiconductors Chapter 14: LPC17xx UART0/2/3 Table 282: UARTn Auto-baud Control Register (U0ACR - address 0x4000 C020, U2ACR - 0x4009 8020, U3ACR 0x4009 C020) bit description Bit Symbol 8 9 Description Reset value ABEOIntClr End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. 0 ABTOIntClr Auto-baud time-out interrupt clear bit (write-only accessible).
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UM10360 NXP Semiconductors Chapter 14: LPC17xx UART0/2/3 (1) 2 × P CLK PCLK ratemin = ------------------------- ≤ UART n baudrate ≤ ------------------------------------------------------------------------------------------------------------ = ratemax 16 × 2 15 14.4.10.2 16 × ( 2 + databits + paritybits + stopbits ) Auto-baud modes When the software is expecting an “AT” command, it configures the UARTn with the expected character format and sets the UnACR Start bit.
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UM10360 NXP Semiconductors Chapter 14: LPC17xx UART0/2/3 'A' (0x41) or 'a' (0x61) start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop UARTn RX start bit LSB of 'A' or 'a' UnACR start rate counter 16xbaud_rate 16 cycles 16 cycles a. Mode 0 (start bit and LSB are used for auto-baud) 'A' (0x41) or 'a' (0x61) start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop UARTn RX start bit LSB of 'A' or 'a' UnACR start rate counter 16xbaud_rate 16 cycles b.
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UM10360 NXP Semiconductors Chapter 14: LPC17xx UART0/2/3 Table 283: UARTn IrDA Control Register (U0ICR - 0x4000 C024, U2ICR - 0x4009 8024, U3ICR - 0x4009 C024) bit description Bit Symbol 2 FixPulseEn 5:3 PulseDiv 31:6 - Value Description NA Reset value When 1, enabled IrDA fixed pulse width mode. 0 Configures the pulse when FixPulseEn = 1. See text below for details. 0 Reserved, user software should not write ones to reserved bits. The value read 0 from a reserved bit is not defined.
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UM10360 NXP Semiconductors Chapter 14: LPC17xx UART0/2/3 This register controls the clock pre-scaler for the baud rate generation. The reset value of the register keeps the fractional capabilities of UART0/2/3 disabled making sure that UART0/2/3 is fully software and hardware compatible with UARTs not equipped with this feature.
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UM10360 NXP Semiconductors Chapter 14: LPC17xx UART0/2/3 Calculating UART baudrate (BR) PCLK, BR DL est = PCLK/(16 x BR) DL est is an integer? True False DIVADDVAL = 0 MULVAL = 1 FR est = 1.5 Pick another FR est from the range [1.1, 1.9] DL est = Int(PCLK/(16 x BR x FR est)) FR est = PCLK/(16 x BR x DL est) False 1.1 < FR est < 1.9? True DIVADDVAL = table(FR est ) MULVAL = table(FR est ) DLM = DL est [15:8] DLL = DLest [7:0] End Fig 46.
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UM10360 NXP Semiconductors Chapter 14: LPC17xx UART0/2/3 Table 286. Fractional Divider setting look-up table 14.4.12.1.1 FR DivAddVal/ MulVal FR DivAddVal/ MulVal FR DivAddVal/ MulVal FR DivAddVal/ MulVal 1.000 0/1 1.250 1/4 1.500 1/2 1.750 3/4 1.067 1/15 1.267 4/15 1.533 8/15 1.769 10/13 1.071 1/14 1.273 3/11 1.538 7/13 1.778 7/9 1.077 1/13 1.286 2/7 1.545 6/11 1.786 11/14 1.083 1/12 1.300 3/10 1.556 5/9 1.800 4/5 1.091 1/11 1.308 4/13 1.571 4/7 1.
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UM10360 NXP Semiconductors Chapter 14: LPC17xx UART0/2/3 Table 287 describes how to use TXEn bit in order to achieve software flow control. Table 287: UARTn Transmit Enable Register (U0TER - address 0x4000 C030, U2TER - 0x4009 8030, U3TER 0x4009 C030) bit description Bit Symbol Description Reset Value 6:0 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
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UM10360 NXP Semiconductors Chapter 14: LPC17xx UART0/2/3 Transmitter Transmitter Holding Register Transmitter FIFO Transmitter Shift Register Un_TXD Transmitter DMA Interface TX_DMA_REQ TX_DMA_CLR Baud Rate Generator Fractional Main Rate Divider Divider (DLM, DLL) PCLK FIFO Control & Status Interrupt UARTn interrupt Control & Status Line Control & Status Un_OE IrDA, & Autobaud Receiver Receiver Buffer Register Receiver FIFO Receiver Shift Register Un_RXD Receiver DMA Interface RX_DMA_REQ RX_D
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UM10360 Chapter 15: LPC17xx UART1 Rev. 2 — 19 August 2010 User manual 15.1 Basic configuration The UART1 peripheral is configured using the following registers: 1. Power: In the PCONP register (Table 46), set bits PCUART1. Remark: On reset, UART1 is enabled (PCUART1 = 1). 2. Peripheral clock: In the PCLKSEL0 register (Table 40), select PCLK_UART1. 3. Baud rate: In register U1LCR (Table 298), set bit DLAB =1. This enables access to registers DLL (Table 292) and DLM (Table 293) for setting the baud rate.
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UM10360 NXP Semiconductors Chapter 15: LPC17xx UART1 15.3 Pin description Table 288: UART1 Pin Description Pin Type RXD1 Input Description Serial Input. Serial receive data. TXD1 Output Serial Output. Serial transmit data. CTS1 Input Clear To Send. Active low signal indicates if the external modem is ready to accept transmitted data via TXD1 from the UART1. In normal operation of the modem interface (U1MCR[4] = 0), the complement value of this signal is stored in U1MSR[4].
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UM10360 NXP Semiconductors Chapter 15: LPC17xx UART1 15.4 Register description UART1 contains registers organized as shown in Table 289. The Divisor Latch Access Bit (DLAB) is contained in U1LCR[7] and enables access to the Divisor Latches. Table 289: UART1 register map Name Description Access Reset Address Value[1] U1RBR Receiver Buffer Register. Contains the next received character to be read. RO NA 0x4001 0000 (when DLAB=0) Transmit Holding Register.
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UM10360 NXP Semiconductors Chapter 15: LPC17xx UART1 15.4.1 UART1 Receiver Buffer Register (U1RBR - 0x4001 0000, when DLAB = 0) The U1RBR is the top byte of the UART1 RX FIFO. The top byte of the RX FIFO contains the oldest character received and can be read via the bus interface. The LSB (bit 0) represents the “oldest” received data bit. If the character received is less than 8 bits, the unused MSBs are padded with zeroes.
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UM10360 NXP Semiconductors Chapter 15: LPC17xx UART1 Table 292: UART1 Divisor Latch LSB Register (U1DLL - address 0x4001 0000 when DLAB = 1) bit description Bit Symbol Description Reset Value 7:0 DLLSB The UART1 Divisor Latch LSB Register, along with the U1DLM register, determines the baud rate of the UART1. 0x01 31:8 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
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UM10360 NXP Semiconductors Chapter 15: LPC17xx UART1 Table 294: UART1 Interrupt Enable Register (U1IER - address 0x4001 0004 when DLAB = 0) bit description Bit Symbol 8 ABEOIntEn 9 Value Description Reset Value Enables the end of auto-baud interrupt. 0 Disable end of auto-baud Interrupt. 1 Enable end of auto-baud Interrupt. ABTOIntEn 0 Enables the auto-baud time-out interrupt. 0 0 Disable auto-baud time-out Interrupt. 1 Enable auto-baud time-out Interrupt.
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UM10360 NXP Semiconductors Chapter 15: LPC17xx UART1 interrupt handler routine can determine the cause of the interrupt and how to clear the active interrupt. The U1IIR must be read in order to clear the interrupt prior to exiting the Interrupt Service Routine. The UART1 RLS interrupt (U1IIR[3:1] = 011) is the highest priority interrupt and is set whenever any one of four error conditions occur on the UART1RX input: overrun error (OE), parity error (PE), framing error (FE) and break interrupt (BI).
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UM10360 NXP Semiconductors Chapter 15: LPC17xx UART1 The UART1 THRE interrupt (U1IIR[3:1] = 001) is a third level interrupt and is activated when the UART1 THR FIFO is empty provided certain initialization conditions have been met. These initialization conditions are intended to give the UART1 THR FIFO a chance to fill up with data to eliminate many THRE interrupts from occurring at system start-up.
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UM10360 NXP Semiconductors Chapter 15: LPC17xx UART1 UART receiver DMA In DMA mode, the receiver DMA request is asserted on the event of the receiver FIFO level becoming equal to or greater than trigger level, or if a character timeout occurs. See the description of the RX Trigger Level above. The receiver DMA request is cleared by the DMA controller. UART transmitter DMA In DMA mode, the transmitter DMA request is asserted on the event of the transmitter FIFO transitioning to not full.
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UM10360 NXP Semiconductors Chapter 15: LPC17xx UART1 Table 299: UART1 Modem Control Register (U1MCR - address 0x4001 0010) bit description Bit Symbol 0 DTR Control Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode 0 is active. 1 RTS Control Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is 0 active.
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UM10360 NXP Semiconductors Chapter 15: LPC17xx UART1 If Auto-RTS mode is disabled, the RTSen bit controls the RTS1 output of the UART1. If Auto-RTS mode is enabled, hardware controls the RTS1 output, and the actual value of RTS1 will be copied in the RTS Control bit of the UART1. As long as Auto-RTS is enabled, the value of the RTS Control bit is read-only for software.
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UM10360 NXP Semiconductors Chapter 15: LPC17xx UART1 ~ ~ UART1 TX bits0..7 stop start bits0..7 stop start bits0..7 stop ~ ~ start ~ ~ The auto-CTS function reduces interrupts to the host system. When flow control is enabled, a CTS1 state change does not trigger host interrupts because the device automatically controls its own transmitter. Without Auto-CTS, the transmitter sends any data present in the transmit FIFO and a receiver overrun error can result.
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UM10360 NXP Semiconductors Chapter 15: LPC17xx UART1 Table 301: UART1 Line Status Register (U1LSR - address 0x4001 0014) bit description Bit Symbol 3 Framing Error (FE) Value Description Reset Value 0 When the stop bit of a received character is a logic 0, a framing error occurs. An U1LSR read clears U1LSR[3]. The time of the framing error detection is dependent on U1FCR0.
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UM10360 NXP Semiconductors Chapter 15: LPC17xx UART1 Table 302: UART1 Modem Status Register (U1MSR - address 0x4001 0018) bit description Bit Symbol Value Description 1 Delta DSR Set upon state change of input DSR. Cleared on an U1MSR read. 0 1 2 3 Reset Value Trailing Edge RI 0 No change detected on modem input, DSR. State change detected on modem input, DSR. Set upon low to high transition of input RI. Cleared on an U1MSR read. 0 No change detected on modem input, RI.
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UM10360 NXP Semiconductors Chapter 15: LPC17xx UART1 Table 304: Auto-baud Control Register (U1ACR - address 0x4001 0020) bit description Bit Symbol Value Description Reset value 2 AutoRestart 0 No restart 0 1 Restart in case of time-out (counter restarts at next UART1 Rx falling edge) 0 NA Reserved, user software should not write ones to reserved bits. The value read 0 from a reserved bit is not defined. 7:3 - 8 ABEOIntClr 9 End of auto-baud interrupt clear bit (write-only accessible).
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UM10360 NXP Semiconductors Chapter 15: LPC17xx UART1 register is not going to be modified after rate measurement. Also, when auto-baud is used, any write to U1DLM and U1DLL registers should be done before U1ACR register write. The minimum and the maximum baud rates supported by UART1 are function of pclk, number of data bits, stop bits and parity bits.
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UM10360 NXP Semiconductors Chapter 15: LPC17xx UART1 'A' (0x41) or 'a' (0x61) start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop UARTn RX start bit LSB of 'A' or 'a' U0ACR start rate counter 16xbaud_rate 16 cycles 16 cycles a. Mode 0 (start bit and LSB are used for auto-baud) 'A' (0x41) or 'a' (0x61) start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop UARTn RX start bit LSB of 'A' or 'a' U1ACR start rate counter 16xbaud_rate 16 cycles b.
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UM10360 NXP Semiconductors Chapter 15: LPC17xx UART1 Table 305: UART1 Fractional Divider Register (U1FDR - address 0x4001 0028) bit description Bit Function Value Description Reset value 3:0 DIVADDVAL 0 Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate. 0 7:4 MULVAL 1 Baud-rate pre-scaler multiplier value.
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UM10360 NXP Semiconductors Chapter 15: LPC17xx UART1 Calculating UART baudrate (BR) PCLK, BR DL est = PCLK/(16 x BR) DL est is an integer? True False DIVADDVAL = 0 MULVAL = 1 FR est = 1.5 Pick another FR est from the range [1.1, 1.9] DL est = Int(PCLK/(16 x BR x FR est)) FR est = PCLK/(16 x BR x DL est) False 1.1 < FR est < 1.9? True DIVADDVAL = table(FR est ) MULVAL = table(FR est ) DLM = DL est [15:8] DLL = DLest [7:0] End Fig 51.
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UM10360 NXP Semiconductors Chapter 15: LPC17xx UART1 Table 306. Fractional Divider setting look-up table 15.4.16.1.1 FR DivAddVal/ MulVal FR DivAddVal/ MulVal FR DivAddVal/ MulVal FR DivAddVal/ MulVal 1.000 0/1 1.250 1/4 1.500 1/2 1.750 3/4 1.067 1/15 1.267 4/15 1.533 8/15 1.769 10/13 1.071 1/14 1.273 3/11 1.538 7/13 1.778 7/9 1.077 1/13 1.286 2/7 1.545 6/11 1.786 11/14 1.083 1/12 1.300 3/10 1.556 5/9 1.800 4/5 1.091 1/11 1.308 4/13 1.571 4/7 1.
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UM10360 NXP Semiconductors Chapter 15: LPC17xx UART1 Although Table 307 describes how to use TxEn bit in order to achieve hardware flow control, it is strongly suggested to let UART1 hardware implemented auto flow control features take care of this, and limit the scope of TxEn to software flow control. U1TER enables implementation of software and hardware flow control. When TXEn=1, UART1 transmitter will keep sending data as long as they are available.
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UM10360 NXP Semiconductors Chapter 15: LPC17xx UART1 Table 308: UART1 RS485 Control register (U1RS485CTRL - address 0x4001 004C) bit description Bit Symbol 5 OINV 31:6 - Value Description Reset value This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin. 0 0 The direction control pin will be driven to logic ‘0’ when the transmitter has data to be sent. It will be driven to logic ‘1’ after the last bit of data has been transmitted.
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UM10360 NXP Semiconductors Chapter 15: LPC17xx UART1 If the receiver is DISABLED (RS485CTRL bit 1 = ‘1’) any received data bytes will be ignored and will not be stored in the RXFIFO. When an address byte is detected (parity bit = ‘1’) it will be placed into the RXFIFO and an Rx Data Ready Interrupt will be generated. The processor can then read the address byte and decide whether or not to enable the receiver to accept the following data.
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UM10360 NXP Semiconductors Chapter 15: LPC17xx UART1 RS485/EIA-485 output inversion The polarity of the direction control signal on the RTS (or DTR) pins can be reversed by programming bit 5 in the U1RS485CTRL register. When this bit is set, the direction control pin will be driven to logic 1 when the transmitter has data waiting to be sent. The direction control pin will be driven to logic 0 after the last bit of data has been transmitted. 15.
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UM10360 NXP Semiconductors Chapter 15: LPC17xx UART1 Transmitter Transmitter Holding Register Transmitter FIFO Transmitter Shift Register U1_TXD Transmitter DMA Interface TX_DMA_REQ TX_DMA_CLR Baud Rate Generator Fractional Main Rate Divider Divider (DLM, DLL) PCLK UART1 interrupt U1_CTS U1_RTS U1_DSR U1_DTR U1_DCD U1_RI Modem Control & Status FIFO Control & Status Interrupt Control & Status U1_OE Line Control & Status RS485, IrDA, & Auto-baud Receiver Receiver Buffer Register Receiver FIFO
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UM10360 Chapter 16: LPC17xx CAN1/2 Rev. 2 — 19 August 2010 User manual 16.1 Basic configuration The CAN1/2 peripherals are configured using the following registers: 1. Power: In the PCONP register (Table 46), set bits PCAN1/2. Remark: On reset, the CAN1/2 blocks are disabled (PCAN1/2 = 0). 2. Peripheral clock: In the PCLKSEL0 register (Table 40), select PCLK_CAN1, PCLK_CAN2, and, for the acceptance filter, PCLK_ACF. Note that these must all be the same value.
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 • • • • • • Guaranteed latency time for high priority messages. Programmable transfer rate (up to 1 Mbit/s). Multicast and broadcast message facility. Data length from 0 up to 8 bytes. Powerful error handling capability. Non-return-to-zero (NRZ) encoding/decoding with bit stuffing. 16.3.2 CAN controller features • • • • • • • • 2 CAN controllers and buses. Supports 11-bit identifier as well as 29-bit identifier.
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 • Nested Vectored Interrupt Controller (NVIC) • CAN Transceiver • Common Status Registers INTERFACE MANAGEMENT LOGIC APB BUS CAN CORE BLOCK TX ERROR MANAGEMENT LOGIC NVIC TRANSMIT BUFFERS 1,2 AND 3 COMMON STATUS REGISTER ACCEPTANCE FILTER RX CAN TRANSCEIVER BIT TIMING LOGIC BIT STREAM PROCESSOR RECEIVE BUFFERS 1 AND 2 Fig 53. CAN controller block diagram 16.5.
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 31 24 23 TX Frame info 16 15 unused TX DLC 87 unused 0 . . . 0 0 TX Priority TFS ID.28 ... ID.18 TID TX Data 4 TX Data 3 TX Data 2 TX Data 1 TDA TX Data 8 TX Data 7 TX Data 6 TX Data 5 TDB Descriptor Field Data Field Standard Frame Format (11-bit Identifier) 31 24 23 TX Frame info 000 16 15 unused TX DLC ID.28 87 unused ... 0 TX Priority TFS ID.
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 31 24 23 RX Frame info 16 15 unused RX DLC 10 9 8 7 unused unused 0 ID Index RFS ID.28 ... ID.18 RID RX Data 4 RX Data 3 RX Data 2 RX Data 1 RDA RX Data 8 RX Data 7 RX Data 6 RX Data 5 RDB Descriptor Field Data Field BPM=bypass message Standard Frame Format (11-bit Identifier) 31 24 23 RX Frame info unused 16 15 unused RX DLC ID.28 10 9 8 7 unused 0 ID Index ... RFS ID.
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 Both self-tests are using the ‘Self Reception’ feature of the CAN Controller. With the Self Reception Request, the transmitted message is also received and stored in the receive buffer. Therefore the acceptance filter has to be configured accordingly. As soon as the CAN message is transmitted, a transmit and a receive interrupt are generated, if enabled.
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 16.6 Memory map of the CAN block The CAN Controllers and Acceptance Filter occupy a number of APB slots, as follows: Table 312. Memory map of the CAN block Address Range Used for 0x4003 8000 - 0x4003 87FF Acceptance Filter RAM. 0x4003 C000 - 0x4003 C017 Acceptance Filter Registers. 0x4004 0000 - 0x4004 000B Central CAN Registers. 0x4004 4000 - 0x4004 405F CAN Controller 1 Registers. 0x4004 8000 - 0x4004 805F CAN Controller 2 Registers.
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 Table 314.
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 The internal registers of each CAN Controller appear to the CPU as on-chip memory mapped peripheral registers. Because the CAN Controller can operate in different modes (Operating/Reset, see also Section 16.7.1 “CAN Mode register (CAN1MOD 0x4004 4000, CAN2MOD - 0x4004 8000)”), one has to distinguish between different internal address definitions. Note that write access to some registers is only allowed in Reset Mode. Table 315.
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 Table 317. CAN Mode register (CAN1MOD - address 0x4004 4000, CAN2MOD - address 0x4004 8000) bit description Bit Symbol Value Function Reset RM Value Set 0 RM[1][6] Reset Mode. 1 1 0 x 0 x 0 x 0 0 0 x 0 (normal) The CAN Controller is in the Operating Mode, and certain registers can not be written. 1 (reset) CAN operation is disabled, writable registers can be written and the current transmission/reception of a message is aborted.
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 [3] A write access to the bits MOD.1 and MOD.2 is possible only if the Reset Mode is entered previously. [4] Transmit Priority Mode is explained in more detail in Section 16.5.3 “Transmit Buffers (TXB)”. [5] The CAN Controller will enter Sleep Mode, if the Sleep Mode bit is set '1' (sleep), there is no bus activity, and none of the CAN interrupts is pending.
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 Table 318. CAN Command Register (CAN1CMR - address 0x4004 4004, CAN2CMR - address 0x4004 8004) bit description Bit Symbol Value Function Reset RM Value Set 5 STB1 Select Tx Buffer 1. 0 0 0 0 0 0 6 0 (not selected) Tx Buffer 1 is not selected for transmission. 1 (selected) Tx Buffer 1 is selected for transmission. STB2 7 Select Tx Buffer 2. 0 (not selected) Tx Buffer 2 is not selected for transmission.
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 Table 319. CAN Global Status Register (CAN1GSR - address 0x4004 4008, CAN2GSR - address 0x4004 8008) bit description Bit Symbol Value Function Reset RM Value Set 0 RBS[1] Receive Buffer Status. 0 0 0 0 1 1 1 x 1 0 1 0 0 0 0 0 0 (empty) No message is available.
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 [2] If there is not enough space to store the message within the Receive Buffer, that message is dropped and the Data Overrun condition is signalled to the CPU in the moment this message becomes valid. If this message is not completed successfully (e.g. because of an error), no overrun condition is signalled.
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 until the Reset Mode is cancelled again. After leaving the Reset Mode, the new TX Counter content is interpreted and the Bus Off event is performed in the same way as if it was forced by a bus error event. That means, that the Reset Mode is entered again, the TX Error Counter is initialized to 127, the RX Counter is cleared, and all concerned Status and Interrupt Register bits are set.
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 Table 320. CAN Interrupt and Capture Register (CAN1ICR - address 0x4004 400C, CAN2ICR - address 0x4004 800C) bit description Bit Symbol Value Function Reset RM Value Set 5 EPI 0 (reset) 1 (set) Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and the CAN controller switches between Error Passive and Error Active mode in either direction.
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 Table 320. CAN Interrupt and Capture Register (CAN1ICR - address 0x4004 400C, CAN2ICR - address 0x4004 800C) bit description Bit Symbol Value 20:16 ERRBIT 4:0[3] 21 00011 Start of Frame 00010 ID28 ... ID21 00110 ID20 ... ID18 00100 SRTR Bit 00101 IDE bit 00111 ID17 ... 13 01111 ID12 ... ID5 01110 ID4 ...
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 Table 320. CAN Interrupt and Capture Register (CAN1ICR - address 0x4004 400C, CAN2ICR - address 0x4004 800C) bit description Bit Symbol Value 31:24 ALCBIT[4] - 00 Function Reset RM Value Set Each time arbitration is lost while trying to send on the CAN, the bit number within the frame is captured into this field. After the content of ALCBIT is read, the ALI bit is cleared and a new Arbitration Lost interrupt can occur.
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 Table 321. CAN Interrupt Enable Register (CAN1IER - address 0x4004 4010, CAN2IER - address 0x4004 8010) bit description Bit Symbol Function 3 DOIE Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status Register), the 0 CAN Controller requests the respective interrupt. X 4 WUIE Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the respective interrupt is requested.
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 Table 322. CAN Bus Timing Register (CAN1BTR - address 0x4004 4014, CAN2BTR - address 0x4004 8014) bit description Bit Symbol Value Function 23 SAM 31:24 - Reset RM Value Set Sampling 0 The bus is sampled once (recommended for high speed buses) 0 1 The bus is sampled 3 times (recommended for low to medium speed buses to filter spikes on the bus-line) X Reserved, user software should not write ones to reserved bits.
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 Table 323. CAN Error Warning Limit register (CAN1EWL - address 0x4004 4018, CAN2EWL - address 0x4004 8018) bit description Bit Symbol Function Reset Value RM Set 7:0 EWL During CAN operation, this value is compared to both the Tx and Rx Error Counters. If either of these counter matches this value, the Error Status (ES) bit in CANSR is set. 9610 = 0x60 X 31:8 - Reserved, user software should not write ones to reserved bits.
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 Table 324. CAN Status Register (CAN1SR - address 0x4004 401C, CAN2SR - address 0x4004 801C) bit description Bit Symbol Value Function Reset RM Value Set 10 TBS2[1] Transmit Buffer Status 2. 1 1 1 x 0(locked) Software cannot access the Tx Buffer 2 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process.
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 16.7.9 CAN Receive Frame Status register (CAN1RFS - 0x4004 4020, CAN2RFS - 0x4004 8020) This register defines the characteristics of the current received message. It is read-only in normal operation but can be written for testing purposes if the RM bit in CANxMOD is 1. Table 325.
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 Table 326. CAN Receive Identifier register (CAN1RID - address 0x4004 4024, CAN2RID - address 0x4004 8024) bit description Bit Symbol Function Reset Value RM Set 10:0 ID The 11-bit Identifier field of the current received message. In CAN 2.0A, these bits are called ID10-0, while in CAN 2.0B they’re called ID29-18. 0 X Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 Table 329. CAN Receive Data register B (CAN1RDB - address 0x4004 402C, CAN2RDB - address 0x4004 802C) bit description Bit Symbol Function Reset Value RM Set 15:8 Data 6 If the DLC field in CANRFS ≥ 0110, this contains the first Data byte of the current 0 received message. X 23:16 Data 7 If the DLC field in CANRFS ≥ 0111, this contains the first Data byte of the current 0 received message.
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 Automatic transmit priority detection To allow uninterrupted streams of transmit messages, the CAN Controller provides Automatic Transmit Priority Detection for all Transmit Buffers. Depending on the selected Transmit Priority Mode, internal prioritization is based on the CAN Identifier or a user defined "local priority".
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 Table 332. Transfer Identifier register when FF = 1 Bit Symbol 28:0 ID 31:29 - Function Reset Value RM Set The 29-bit Identifier to be sent in the next transmit message. 0 X Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 16.7.
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 Table 335. CAN Sleep Clear register (CANSLEEPCLR - address 0x400F C110) bit description Bit Symbol Function Reset Value 0 - Reserved, user software should not write ones to reserved bits. The value read from a NA reserved bit is not defined. 1 CAN1SLEEP Sleep status and control for CAN channel 1. 0 Read: when 1, indicates that CAN channel 1 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 1.
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 recessive bits). Software can monitor this countdown by reading the Tx Error Counter. When this countdown is complete, the CAN Controller clears BS and ES in CANxSR, and sets EI in CANxSR if EIE in IER is 1. The Tx and Rx error counters can be written if RM in CANxMOD is 1. Writing 255 to the Tx Error Counter forces the CAN Controller to Bus-Off state.
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 16.9 Centralized CAN registers For easy and fast access, all CAN Controller Status bits from each CAN Controller Status register are bundled together. Each defined byte of the following registers contains one particular status bit from each of the CAN controllers, in its LS bits. All Status registers are read-only and allow byte, half word and word access. 16.9.1 Central Transmit Status Register (CANTxSR - 0x4004 0000) Table 337.
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 16.9.3 Central Miscellaneous Status Register (CANMSR - 0x4004 0008) Table 339.
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 16.11.1 Acceptance filter Off mode The Acceptance Filter Off Mode is typically used during initialization. During this mode an unconditional access to all registers and to the Look-up Table RAM is possible. With the Acceptance Filter Off Mode, CAN messages are not accepted and therefore not stored in the Receive Buffers of active CAN Controllers. 16.11.
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 16.13 ID look-up table RAM The Whole ID Look-up Table RAM is only word accessible. A write access is only possible during the Acceptance Filter Off or Bypass Mode. Read access is allowed in all Acceptance Filter Modes. If Standard (11-bit) Identifiers are used in the application, at least one of 3 tables in Acceptance Filter RAM must not be empty.
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 31 29 28 0 CONTROLLER # IDENTIFIER Fig 60. Entry in either extended identifier table The table of ranges of Extended Identifiers must contain an even number of entries, of the same form as in the individual Extended Identifier table. Like the Individual Extended table, the Extended Range must be arranged in ascending numerical order.
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 16.14 Acceptance filter registers 16.14.1 Acceptance Filter Mode Register (AFMR - 0x4003 C000) The AccBP and AccOff bits of the acceptance filter mode register are used for putting the acceptance filter into the Bypass and Off mode. The eFCAN bit of the mode register can be used to activate a FullCAN mode enhancement for received 11-bit CAN ID messages. Table 342.
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 16.14.3 Standard Frame Individual Start Address register (SFF_sa 0x4003 C004) Table 343. Standard Frame Individual Start Address register (SFF_sa - address 0x4003 C004) bit description Bit Symbol Description Reset Value 1:0 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 10:2 SFF_sa[1] The start address of the table of individual Standard Identifiers in AF Lookup RAM.
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 [1] Write access to the look-up table section configuration registers are possible only during the Acceptance filter bypass mode or the Acceptance filter off mode. 16.14.6 Extended Frame Group Start Address register (EFF_GRP_sa 0x4003 C010) Table 346. Extended Frame Group Start Address register (EFF_GRP_sa - address 0x4003 C010) bit description Bit Symbol Description 1:0 - Reserved, user software should not write ones to reserved bits.
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 information under which address during an ID screening an error in the look-up table was encountered. Any read of the LUTerrorAddr Filter block can be used for a look-up table interrupt. 16.14.9 LUT Error Address register (LUTerrAd - 0x4003 C018) Table 348. LUT Error Address register (LUTerrAd - address 0x4003 C018) bit description Bit Symbol Description Reset Value 1:0 - Reserved, user software should not write ones to reserved bits.
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 Table 352. FullCAN Interrupt and Capture register 1 (FCANIC1 - address 0x4003 C028) bit description Bit Symbol Description Reset Value 0 IntPnd32 FullCan Interrupt Pending bit 32. 0 ... IntPndx (32
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 Message disable bit Message disable bit Index 0, 1 SCC = 1 0 ID = 0x5A SCC = 1 0 ... Index 2, 3 SCC = 2 0 ... SCC = 3 0 ... Index 4, 5 SCC = 4 0 ... SCC = 5 0 ... Index 6, 7 SCC = 6 0 ... SCC = 6 0 ... Index 8, 9 SCC = 1 0 ID = 0x5A SCC = 1 0 ... Index 10, 11 SCC = 2 0 ... SCC = 3 0 ... Index 12, 13 SCC = 4 0 ... SCC = 5 0 ...
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 receive interrupt whenever a CAN message is accepted and received. Software has to move the received message out of the receive buffer from the according CAN controller into the user RAM. To cover dashboard like applications where the controller typically receives data from several CAN channels for further processing, the CAN Gateway block was extended by a so-called FullCAN receive function.
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 16.16.1 FullCAN message layout Table 353. Format of automatically stored Rx messages Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 SEM [1:0] 0000 DLC 00000 8 7 6 5 0 F R 0000 F T R +4 Rx Data 4 Rx Data 3 Rx Data 2 Rx Data 1 +8 Rx Data 8 Rx Data 7 Rx Data 6 Rx Data 5 4 3 2 1 0 ID.28 ... ID.18 The FF, RTR, and DLC fields are as described in Table 325.
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 START read 1st word SEM == 01? this message has not been received since last check SEM == 11? clear SEM, write back 1st word read 2nd and 3rd words read 1st word SEM == 00? most recently read 1st, 2nd, and 3rd words are from the same message Fig 62. Semaphore procedure for reading an auto-stored message UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 August 2010 © NXP B.V. 2010.
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 16.16.2 FullCAN interrupts The CAN Gateway Block contains a 2 kB ID Look-up Table RAM. With this size a maximum number of 146 FullCAN objects can be defined if the whole Look-up Table RAM is used for FullCAN objects only. Only the first 64 FullCAN objects can be configured to participate in the interrupt scheme. It is still possible to define more than 64 FullCAN objects.
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 Message disable bit Message disable bit 3 1 0 2 9 8 7 6 5 4 3 2 1 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 Index 0, 1 SCC 0 11-bit CAN ID SCC 0 11-bit CAN ID Index 2, 3 SCC 0 11-bit CAN ID SCC 0 11-bit CAN ID Index 4, 5 SCC 0 11-bit CAN ID SCC 0 11-bit CAN ID Index 6, 7 SCC 0 11-bit CAN ID SCC 0 11-bit CAN ID New: FullCAN Message Interrupt enable bit 3 2 1 0 FullCAN Explicit Standard Frame Form
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 16.16.2.3 Setting the interrupt pending bits (IntPnd 63 to 0) The interrupt pending bit (IntPndx) gets asserted in case of an accepted FullCAN message and if the interrupt of the according FullCAN Object is enabled (enable bit FCANIntxEn) is set). During the last write access from the data storage of a FullCAN message object the interrupt pending bit of a FullCAN object (IntPndx) gets asserted. 16.16.2.
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 semaphore bits 01 11 00 IntPndx look-up table access Write ID, SEM write D1 write D2 write SEM read clear SEM SEM read D1 read read D2 SEM MsgLostx message handler access ARM processor access Fig 65. Normal case, no messages lost 16.16.3.2 Scenario 2: Message lost In this scenario a first FullCAN Message is stored and read out by Software (1st Object write and read).
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 16.16.3.3 Scenario 3: Message gets overwritten indicated by Semaphore bits This scenario is a special case in which the lost message is indicated by the existing semaphore bits. The scenario is entered, if during a Software read of a message object another new message gets stored by the message handler. In this case, the FullCAN Interrupt bit gets set for a second time with the 2nd Object write.
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 semaphore bits 01 11 00 01 11 00 IntPndx write write write write ID, D1 D2 SEM SEM look-up table access 1st Object write read clear SEM SEM write write write write ID, D1 D2 SEM SEM read read read D1 D2 SEM clear SEM read read read D1 D2 SEM 2nd Object write 2nd Object read 1st Object read Interrupt Service Routine MsgLostx message handler access ARM processor access Fig 68.
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 semaphore bits 01 11 01 11 00 01 11 IntPndx write write write write read ID, D1 D2 SEM SEM SEM look-up table access 1st Object write write write write write ID, D1 D2 SEM SEM clear SEM read read read D1 D2 SEM 2nd Object write write write write write ID, D1 D2 SEM SEM 3rd Object write 1st Object read Interrupt Service Routine MsgLostx message handler access ARM processor access Fig 69.
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 semaphore bits 01 11 01 11 11 00 IntPndx write write write write ID, D1 D2 SEM SEM look-up table access 1st Object write write write write write ID, D1 D2 SEM SEM read clear SEM SEM read read read D1 D2 SEM write write write write ID, D1 D2 SEM SEM 2nd Object write 3rd Object write 1st Object read MsgLostx message handler access ARM processor access Fig 70. Clearing message lost 16.
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 In cases where explicit identifiers as well as groups of the identifiers are programmed, a CAN identifier search has to start in the explicit identifier section first. If no match is found, it continues the search in the group of identifier section.
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 000 d := 000 h := 0 0000 0000 b look-up table RAM APB base + address column_lower 00d = 00h 0 1 04d = 04h 2 3 44d = 2Ch 22 23 48d = 30h 24 25 column_upper 2 6 52d = 34h ID index # 0 1 2 3 22 23 24 25 explicit SFF table SFF_sa 26 d 84d = 54h lower_boundary 3 4 upper_boundary 34 d 88d = 58h lower_boundary 3 5 upper_boundary 35 d 92d = 5Ch lower_boundary 3 6 upper_boundary 36 d 100d = 64h 38 38 d 104d = 68h 39 39 d EF
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 Table 356.
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 Message disable bit Message disable bit Index SFF_sa = 0x00 SFF_GRP_sa = 0x10 EFF_sa = 0x20 EFF_GRP_sa = 0x30 Explicit Standard Frame ... Format Identifier Section Group of Standard Frame ...
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 FullCAN explicit standard frame format identifier section (11-bit CAN ID) The start address of the FullCAN Explicit Standard Frame Format Identifier section is (automatically) set to 0x00. The end of this section is defined in the SFF_sa register. In the FullCAN ID section only identifiers of FullCAN Object are stored for acceptance filtering. In this section two CAN Identifiers with their Source CAN Channels (SCC) share one 32-bit word.
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 FullCAN Interrupt Enable bit Message Disable bit FullCAN Explicit Standard Frame ... Format Identifier Section SFF_sa = 0x10 Explicit Standard Frame ...
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UM10360 NXP Semiconductors Chapter 16: LPC17xx CAN1/2 • Each section has to be organized as a sorted list or table with an increasing order of the Source CAN Channel (SCC) in conjunction with the CAN Identifier (there is no exception for disabled identifiers). • The upper and lower bound in a Group of Identifiers definition has to be from the same Source CAN Channel. • To disable a Group of Identifiers the message disable bit has to be set for both, the upper and lower bound.
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UM10360 Chapter 17: LPC17xx SPI Rev. 2 — 19 August 2010 User manual 17.1 Basic configuration The SPI is configured using the following registers: 1. Power: In the PCONP register (Table 46), set bit PCSPI. Remark: On reset, the SPI is enabled (PCSPI = 1). 2. Clock: In the PCLKSEL0 register (Table 40), set bit PCLK_SPI. In master mode, the clock must be an even number greater than or equal to 8 (see Section 17.7.4). 3.
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UM10360 NXP Semiconductors Chapter 17: LPC17xx SPI 17.4 Pin description Table 358. SPI pin description Pin Name Type Pin Description SCK Input/ Output Serial Clock. The SPI clock signal (SCK) is used to synchronize the transfer of data across the SPI interface. The SPI is always driven by the master and received by the slave. The clock is programmable to be active high or active low. The SPI is only active during a data transfer. Any other time, it is either in its inactive state, or tri-stated.
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UM10360 NXP Semiconductors Chapter 17: LPC17xx SPI SCK (CPOL = 0) SCK (CPOL = 1) SSEL CPHA = 0 Cycle # CPHA = 0 1 2 3 4 5 6 7 8 MOSI (CPHA = 0) BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 MISO (CPHA = 0) BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 CPHA = 1 Cycle # CPHA = 1 1 2 3 4 5 6 7 8 MOSI (CPHA = 1) BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 MISO (CPHA = 1) BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 Fig 74.
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UM10360 NXP Semiconductors Chapter 17: LPC17xx SPI 17.6 SPI peripheral details 17.6.1 General information There are five control and status registers for the SPI port. They are described in detail in Section 17.7 “Register description” on page 406. The SPI Control Register (S0SPCR) contains a number of programmable bits used to control the function of the SPI block. The settings for this register must be set up prior to a given data transfer taking place.
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UM10360 NXP Semiconductors Chapter 17: LPC17xx SPI 3. Wait for the SPIF bit in the SPI Status Register to be set to 1. The SPIF bit will be set after the last cycle of the SPI data transfer. 4. Read the SPI Status Register. 5. Read the received data from the SPI Data Register (optional). 6. Go to step 2 if more data is to be transmitted. Note: A read or write of the SPI Data Register is required in order to clear the SPIF status bit.
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UM10360 NXP Semiconductors Chapter 17: LPC17xx SPI Register has been read when the SPIF status is active. If the SPI Data Register is written in this time frame, the write data will be lost, and the write collision (WCOL) bit in the SPI Status Register will be activated. Mode Fault If the SSEL signal goes active when the SPI block is a master, this indicates another master has selected the device to be a slave. This condition is known as a mode fault.
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UM10360 NXP Semiconductors Chapter 17: LPC17xx SPI Table 361: SPI Control Register (S0SPCR - address 0x4002 0000) bit description Bit Symbol 1:0 - 2 BitEnable 3 4 5 Value Description Reserved, user software should not write ones to reserved bits. NA The value read from a reserved bit is not defined. 0 The SPI controller sends and receives 8 bits of data per transfer. 1 The SPI controller sends and receives the number of bits selected by bits 11:8.
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UM10360 NXP Semiconductors Chapter 17: LPC17xx SPI 17.7.2 SPI Status Register (S0SPSR - 0x4002 0004) The S0SPSR register controls the operation of SPI0 as per the configuration bits setting shown in Table 362. Table 362: SPI Status Register (S0SPSR - address 0x4002 0004) bit description Bit Symbol Description Reset Value 2:0 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 3 ABRT Slave abort.
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UM10360 NXP Semiconductors Chapter 17: LPC17xx SPI In Master mode, this register must be an even number greater than or equal to 8. Violations of this can result in unpredictable behavior. The SPI0 SCK rate may be calculated as: PCLK_SPI / SPCCR0 value. The SPI peripheral clock is determined by the PCLKSEL0 register contents for PCLK_SPI as described in Section 4.7.3. In Slave mode, the SPI clock rate provided by the master must not exceed 1/8 of the SPI peripheral clock selected in Section 4.7.3.
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UM10360 NXP Semiconductors Chapter 17: LPC17xx SPI Table 366: SPI Test Status Register (SPTSR - address 0x4002 0014) bit description Bit Symbol Description Reset Value 6 WCOL Write collision. 0 7 SPIF SPI transfer complete flag. 0 31:8 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 17.7.7 SPI Interrupt Register (S0SPINT - 0x4002 001C) This register contains the interrupt flag for the SPI0 interface.
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UM10360 NXP Semiconductors Chapter 17: LPC17xx SPI 17.8 Architecture The block diagram of the SPI solution implemented in SPI0 interface is shown in the Figure 75. MOSI_IN MOSI_OUT MISO_IN MISO_OUT SPI SHIFT REGISTER SPI CLOCK SCK_IN SCK_OUT SS_IN GENERATOR & DETECTOR SPI Interrupt APB Bus SPI REGISTER INTERFACE SPI STATE CONTROL OUTPUT ENABLE LOGIC SCK_OUT_EN MOSI_OUT_EN MISO_OUT_EN Fig 75.
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UM10360 Chapter 18: LPC17xx SSP0/1 Rev. 2 — 19 August 2010 User manual 18.1 Basic configuration The two SSP interfaces, SSP0 and SSP1 are configured using the following registers: 1. Power: In the PCONP register (Table 46), set bit PCSSP0 to enable SSP0 and bit PCSSP1 to enable SSP1. Remark: On reset, both SSP interfaces are enabled (PCSSP0/1 = 1). 2. Clock: In PCLKSEL0 select PCLK_SSP1; in PCLKSEL1 select PCLK_SSP0 (see Section 4.7.3. In master mode, the clock must be scaled down (see Section 18.6.5). 3.
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UM10360 NXP Semiconductors Chapter 18: LPC17xx SSP0/1 18.4 Pin descriptions Table 368. SSP pin descriptions Pin Name Interface pin Type name/function Pin Description SPI SSI Microwire SCK0/1 I/O SSEL0/1 I/O SCK CLK SSEL FS SK Serial Clock. SCK/CLK/SK is a clock signal used to synchronize the transfer of data. It is driven by the master and received by the slave. When the SPI interface is used, the clock is programmable to be active-high or active-low, otherwise it is always active-high.
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UM10360 NXP Semiconductors Chapter 18: LPC17xx SSP0/1 CLK FS DX/DR MSB LSB 4 to 16 bits a. Single frame transfer CLK FS DX/DR MSB LSB MSB 4 to 16 bits LSB 4 to 16 bits b. Continuous/back-to-back frames transfer Fig 76. Texas Instruments Synchronous Serial Frame Format: a) Single and b) Continuous/back-to-back Two Frames Transfer For device configured as a master in this mode, CLK and FS are forced LOW, and the transmit data line DX is tri-stated whenever the SSP is idle.
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UM10360 NXP Semiconductors Chapter 18: LPC17xx SSP0/1 The CPHA control bit selects the clock edge that captures data and allows it to change state. It has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge. When the CPHA phase control bit is 0, data is captured on the first clock edge transition. If the CPHA clock phase control bit is 1, data is captured on the second clock edge transition. 18.5.2.
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UM10360 NXP Semiconductors Chapter 18: LPC17xx SSP0/1 In the case of a single word transmission, after all bits of the data word have been transferred, the SSEL line is returned to its idle HIGH state one SCK period after the last bit has been captured. However, in the case of continuous back-to-back transmissions, the SSEL signal must be pulsed HIGH between each data word transfer.
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UM10360 NXP Semiconductors Chapter 18: LPC17xx SSP0/1 SCK SSEL MSB MOSI MISO LSB MSB LSB Q 4 to 16 bits a. Single transfer with CPOL=1 and CPHA=0 SCK SSEL MOSI MISO MSB LSB MSB LSB MSB Q LSB MSB LSB Q 4 to 16 bits 4 to 16 bits b. Continuous transfer with CPOL=1 and CPHA=0 Fig 79. SPI frame format with CPOL = 1 and CPHA = 0 (a) Single and b) Continuous Transfer) In this configuration, during idle periods: • The CLK signal is forced HIGH. • SSEL is forced HIGH.
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UM10360 NXP Semiconductors Chapter 18: LPC17xx SSP0/1 18.5.2.5 SPI format with CPOL = 1,CPHA = 1 The transfer signal sequence for SPI format with CPOL = 1, CPHA = 1 is shown in Figure 80, which covers both single and continuous transfers. SCK SSEL MOSI MISO Q MSB LSB MSB LSB Q 4 to 16 bits Fig 80. SPI Frame Format with CPOL = 1 and CPHA = 1 In this configuration, during idle periods: • The CLK signal is forced HIGH. • SSEL is forced HIGH. • The transmit MOSI/MISO pad is in high impedance.
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UM10360 NXP Semiconductors Chapter 18: LPC17xx SSP0/1 SK CS SO SI MSB LSB 8-bit control 0 MSB LSB 4 to 16 bits output data Fig 81. Microwire frame format (single transfer) Microwire format is very similar to SPI format, except that transmission is half-duplex instead of full-duplex, using a master-slave message passing technique. Each serial transmission begins with an 8-bit control word that is transmitted from the SSP to the off-chip slave device.
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UM10360 NXP Semiconductors Chapter 18: LPC17xx SSP0/1 SK CS SO LSB MSB LSB 8-bit control SI 0 MSB LSB MSB 4 to 16 bits output data LSB 4 to 16 bits output data Fig 82. Microwire frame format (continuos transfers) 18.5.3.1 Setup and hold time requirements on CS with respect to SK in Microwire mode In the Microwire mode, the SSP slave samples the first bit of receive data on the rising edge of SK after CS has gone LOW.
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UM10360 NXP Semiconductors Chapter 18: LPC17xx SSP0/1 18.6 Register description The register addresses of the SSP controllers addresses are shown in Table 369. Table 369. SSP Register Map [1] Generic Name Description CR0 Access Reset Value[1] SSPn Register Name & Address Control Register 0. Selects the R/W serial clock rate, bus type, and data size. 0 SSP0CR0 - 0x4008 8000 SSP1CR0 - 0x4003 0000 CR1 Control Register 1. Selects master/slave and other modes.
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UM10360 NXP Semiconductors Chapter 18: LPC17xx SSP0/1 Table 370: SSPn Control Register 0 (SSP0CR0 - address 0x4008 8000, SSP1CR0 0x4003 0000) bit description Bit Symbol Value Description Reset Value 3:0 DSS 0000 5:4 6 7 Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.
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UM10360 NXP Semiconductors Chapter 18: LPC17xx SSP0/1 Table 371: SSPn Control Register 1 (SSP0CR1 - address 0x4008 8004, SSP1CR1 0x4003 0004) bit description Bit Symbol Value Description Reset Value 0 LBM 0 1 2 Loop Back Mode. 0 During normal operation. 1 Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively). SSE SSP Enable. 0 0 The SSP controller is disabled.
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UM10360 NXP Semiconductors Chapter 18: LPC17xx SSP0/1 18.6.4 SSPn Status Register (SSP0SR - 0x4008 800C, SSP1SR 0x4003 000C) This read-only register reflects the current status of the SSP controller. Table 373: SSPn Status Register (SSP0SR - address 0x4008 800C, SSP1SR - 0x4003 000C) bit description Bit Symbol Description Reset Value 0 TFE Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not. 1 1 TNF Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not.
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UM10360 NXP Semiconductors Chapter 18: LPC17xx SSP0/1 Table 375: SSPn Interrupt Mask Set/Clear register (SSP0IMSC - address 0x4008 8014, SSP1IMSC - 0x4003 0014) bit description Bit Symbol Description Reset Value 0 RORIM Software should set this bit to enable interrupt when a Receive Overrun 0 occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs.
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UM10360 NXP Semiconductors Chapter 18: LPC17xx SSP0/1 Table 377: SSPn Masked Interrupt Status register (SSPnMIS -address 0x4008 801C, SSP1MIS - 0x4003 001C) bit description Bit Symbol Description Reset Value 0 RORMIS This bit is 1 if another frame was completely received while the RxFIFO 0 was full, and this interrupt is enabled. 1 RTMIS 0 This bit is 1 if the Rx FIFO is not empty, has not been read for a "timeout period", and this interrupt is enabled.
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UM10360 NXP Semiconductors Chapter 18: LPC17xx SSP0/1 Table 379: SSPn DMA Control Register (SSP0DMACR - address 0x4008 8024, SSP1DMACR 0x4003 0024) bit description UM10360 User manual Bit Symbol Description Reset Value 0 Receive DMA Enable (RXDMAE) When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled.
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UM10360 Chapter 19: LPC17xx I2C0/1/2 Rev. 2 — 19 August 2010 User manual 19.1 Basic configuration The I2C0/1/2 interfaces are configured using the following registers: 1. Power: In the PCONP register (Table 46), set bit PCI2C0/1/2. Remark: On reset, all I2C interfaces are enabled (PCI2C0/1/2 = 1). 2. Clock: In PCLKSEL0 select PCLK_I2C0; in PCLKSEL1 select PCLK_I2C1 or PCLK_I2C2 (see Section 4.7.3). 3. Pins: Select I2C0, I2C1, or I2C2 pins through the PINSEL registers.
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UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 • I2C0 is a standard I2C compliant bus interface with open-drain pins. This interface supports functions described in the I2C specification for speeds up to 1 MHz (Fast Mode Plus). This includes multi-master operation and allows powering off this device in a working system while leaving the I2C-bus functional. 19.3 Applications Interfaces to external I2C standard parts, such as serial RAMs, LCDs, tone generators, other microcontrollers, etc. 19.
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UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 pull-up resistor pull-up resistor SDA I 2C bus SCL SDA SCL LPCXXXX OTHER DEVICE WITH I 2C INTERFACE OTHER DEVICE WITH I 2C INTERFACE Fig 84. I2C-bus configuration 19.4.1 I2C FAST Mode Plus Fast Mode Plus is a 1 Mbit/sec transfer rate to communicate with the I2C products which the NXP Semiconductors is now providing.
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UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 Any of the I2C interfaces brought out to pins other than those just mentioned use standard I/O pins. These pins also support I2C operation in fast mode and standard mode. The primary difference is that these pins do not include an analog spike suppression filter that exists on the specialized I2C pads. The I2C interfaces all include a digital filter that can serve the same purpose. 19.
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UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 S SLAVE ADDRESS RW=0 A DATA A A/A DATA P n bytes data transmitted A = Acknowledge (SDA low) from Master to Slave A = Not acknowledge (SDA high) from Slave to Master S = START condition P = STOP condition Fig 85. Format in the Master Transmitter mode 19.6.2 Master Receiver mode In the master receiver mode, data is received from a slave transmitter. The transfer is initiated in the same way as in the master transmitter mode.
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UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 After a repeated START condition, I2C may switch to the master transmitter mode. S SLA R A DATA A DATA A Sr SLA W A DATA A P n bytes data transmitted A = Acknowledge (SDA low) A = Not acknowledge (SDA high) From master to slave S = START condition From slave to master P = STOP condition SLA = Slave Address Sr = Repeated START condition Fig 87. A Master Receiver switches to Master Transmitter after sending repeated START 19.6.
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UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 S SLAVE ADDRESS RW=0 A DATA A A/A DATA P/Sr n bytes data received A = Acknowledge (SDA low) from Master to Slave from Slave to Master A = Not acknowledge (SDA high) S = START condition P = STOP condition Sr = Repeated START condition Fig 88. Format of Slave Receiver mode 19.6.4 Slave Transmitter mode The first byte is received and handled as in the slave receiver mode.
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UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 19.7.1 Input filters and output stages Input signals are synchronized with the internal clock, and spikes shorter than three clocks are filtered out. The output for I2C is a special pad designed to conform to the I2C specification.
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UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 19.7.2 Address Registers, I2ADR0 to I2ADR3 These registers may be loaded with the 7-bit slave address (7 most significant bits) to which the I2C block will respond when programmed as a slave transmitter or receiver. The LSB (GC) is used to enable General Call address (0x00) recognition.
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UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 (1) (1) (2) 1 2 3 (3) SDA line SCL line 4 8 9 ACK (1) Another device transmits serial data. (2) Another device overrules a logic (dotted line) transmitted this I2C master by pulling the SDA line low. Arbitration is lost, and this I2C enters Slave Receiver mode. (3) This I2C is in Slave Receiver mode but still generates clock pulses until the current byte has been transmitted. This I2C will not generate clock pulses for the next byte.
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UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 via the I2C Clock Control Registers. See the description of the I2CSCLL and I2CSCLH registers for details. The output clock pulses have a duty cycle as programmed unless the bus is synchronizing with other SCL clock sources as described above. 19.7.8 Timing and control The timing and control logic generates the timing and control signals for serial byte handling.
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UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 19.8 Register description Each I2C interface contains 16 registers as shown in Table 383 below. Remark: In the LPC17xx, the following registers have been added to support response to multiple addresses in Slave mode and a new Monitor mode: I2ADR1 to 3, I2MASK0 To 3, MMCTRL, and I2DATA_BUFFER. Table 383. I2C register map Generic Name Access Reset I2Cn Name & Address value[1] Description I2CONSET I2C Control Set Register.
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UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 Table 383. I2C register map Generic Name Description Access Reset I2Cn Name & Address value[1] I2ADR2 I2C Slave Address Register 2. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. R/W I2C Slave Address Register 3.
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UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 Table 384. I2C Control Set register (I2CONSET: I2C0, I2C0CONSET - address 0x4001 C000, I2C1, I2C1CONSET - address 0x4005 C000, I2C2, I2C2CONSET - address 0x400A 0000) bit description Bit Symbol Description Reset value 1:0 - Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 2 AA Assert acknowledge flag. 0 3 SI I2C 0 4 STO STOP flag. 5 STA START flag.
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UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 In slave mode, setting this bit can recover from an error condition. In this case, no STOP condition is transmitted to the bus. The hardware behaves as if a STOP condition has been received and it switches to “not addressed” slave receiver mode. The STO flag is cleared by hardware automatically. SI is the I2C Interrupt Flag. This bit is set when the I2C state changes.
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UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 Table 385. I2C Control Clear register (I2CONCLR: I2C0, I2C0CONCLR - 0x4001 C018; I2C1, I2C1CONCLR - 0x4005 C018; I2C2, I2C2CONCLR - 0x400A 0018) bit description Bit Symbol Description 4 - Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. 5 STAC START flag Clear bit. 6 I2ENC I2C interface Disable bit. 31:7 - Reserved. User software should not write ones to reserved bits.
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UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 Table 387. I2C Data register (I2DAT: I2C0, I2C0DAT - 0x4001 C008; I2C1, I2C1DAT 0x4005 C008; I2C2, I2C2DAT - 0x400A 0008) bit description Bit Symbol Description Reset value 7:0 Data This register holds data values that have been received or are to be transmitted. 0 31:8 - Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 19.8.
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UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 Table 388. I2C Monitor mode control register (I2MMCTRL: I2C0, I2C0MMCTRL - 0x4001 C01C; I2C1, I2C1MMCTRL- 0x4005 C01C; I2C2, I2C2MMCTRL- 0x400A 001C) bit description Bit Symbol 2 MATCH_ALL 31:3 [1] - Value Description Reset value Select interrupt register match. 0 0 When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers, I2ADR0 through I2ADR3.
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UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 19.8.6 I2C Data buffer register (I2DATA_BUFFER: I2C0, I2CDATA_BUFFER 0x4001 C02C; I2C1, I2C1DATA_BUFFER- 0x4005 C02C; I2C2, I2C2DATA_BUFFER- 0x400A 002C) In monitor mode, the I2C module may lose the ability to stretch the clock if the ENA_SCL bit is not set. This means that the processor will have a limited amount of time to read the contents of the data received on the bus.
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UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 19.8.8 I2C Mask registers (I2MASK0 to 3: I2C0, I2C0MASK[0, 1, 2, 3] 0x4001 C0[30, 34, 38, 3C]; I2C1, I2C1MASK[0, 1, 2, 3] - address 0x4005 C0[30, 34, 38, 3C]; I2C2, I2C2MASK[0, 1, 2, 3] - address 0x400A 00[30, 34, 38, 3C]) The four mask registers each contain seven active bits (7:1).
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UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 19.8.11 Selecting the appropriate I2C data rate and duty cycle Software must set values for the registers I2SCLH and I2SCLL to select the appropriate data rate and duty cycle. I2SCLH defines the number of PCLK_I2C cycles for the SCL HIGH time, I2SCLL defines the number of PCLK_I2C cycles for the SCL low time.
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UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 19.9 Details of I2C operating modes The four operating modes are: • • • • Master Transmitter Master Receiver Slave Receiver Slave Transmitter Data transfers in each mode of operation are shown in Figure 93, Figure 94, Figure 95, Figure 96, and Figure 97. Table 395 lists abbreviations used in these figures when describing the I2C operating modes. Table 395.
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UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 19.9.1 Master Transmitter mode In the master transmitter mode, a number of data bytes are transmitted to a slave receiver (see Figure 93). Before the master transmitter mode can be entered, I2CON must be initialized as follows: Table 396.
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UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 MT successful transmission to a Slave Receiver S SLA W A DATA A 18H 08H P 28H next transfer started with a Repeated Start condition S SLA W 10H Not Acknowledge received after the Slave address A P R 20H Not Acknowledge received after a Data byte A P to Master receive mode, entry = MR 30H arbitration lost in Slave address or Data byte A OR A other Master continues A OR A 38H arbitration lost and addressed as Slave A o
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UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 19.9.2 Master Receiver mode In the master receiver mode, a number of data bytes are received from a slave transmitter (see Figure 94). The transfer is initialized as in the master transmitter mode. When the START condition has been transmitted, the interrupt service routine must load I2DAT with the 7-bit slave address and the data direction bit (SLA+R). The SI bit in I2CON must then be cleared before the serial transfer can continue.
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UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 MR successful transmission to a Slave transmitter S 08H SLA R A DATA 40H A DATA 50H A P 58H next transfer started with a Repeated Start condition S SLA R 10H Not Acknowledge received after the Slave address A P W 48H to Master transmit mode, entry = MT arbitration lost in Slave address or Acknowledge bit other Master continues A OR A A 38H arbitration lost and addressed as Slave A other Master continues 38H other Mas
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UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 19.9.3 Slave Receiver mode In the slave receiver mode, a number of data bytes are received from a master transmitter (see Figure 95). To initiate the slave receiver mode, I2CON register, the I2ADR registers, and the I2MASK registers must be configured. The values on the four I2ADR registers combined with the values on the four I2MASK registers determines which address(es) the I2C block will respond to when slave functions are enabled.
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UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 reception of the own Slave address and one or more Data bytes all are acknowledged S SLA W A DATA 60H A DATA 80H last data byte received is Not acknowledged A P OR S 80H A0H A P OR S 88H arbitration lost as Master and addressed as Slave A 68H reception of the General Call address and one or more Data bytes GENERAL CALL A DATA 70h A DATA 90h last data byte is Not acknowledged A P OR S 90h A0H A P OR S 98h arbitratio
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UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 19.9.4 Slave Transmitter mode In the slave transmitter mode, a number of data bytes are transmitted to a master receiver (see Figure 96). Data transfer is initialized as in the slave receiver mode. When I2ADR and I2CON have been initialized, the I2C block waits until it is addressed by its own slave address followed by the data direction bit which must be “1” (R) for the I2C block to operate in the slave transmitter mode.
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UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 19.9.5 Detailed state tables The following tables show detailed state information for the four I2C operating modes. Table 398. Master Transmitter mode I2CSTAT Status of the Status I2C-bus and Code hardware Next action taken by I2C hardware Application software response To/From I2DAT To I2CON STA STO SI AA 0x08 A START condition Load SLA+W; clear has been transmitted. STA X 0 0 X SLA+W will be transmitted; ACK bit will be received.
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UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 Table 399. Master Receiver mode I2CSTAT Status of the Status I2C-bus and Code hardware Next action taken by I2C hardware Application software response To/From I2DAT To I2CON STA STO SI AA X 0x08 A START condition Load SLA+R has been transmitted. X 0 0 0x10 A repeated START condition has been transmitted. Load SLA+R or X 0 0 X As above.
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UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 Table 400. Slave Receiver mode I2CSTAT Status of the I2C-bus Status and hardware Code Application software response 0x60 Own SLA+W has been received; ACK has been returned. No I2DAT action X or 0 0 0 Data byte will be received and NOT ACK will be returned. No I2DAT action X 0 0 1 Data byte will be received and ACK will be returned. Arbitration lost in SLA+R/W as master; Own SLA+W has been received, ACK returned.
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UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 Table 400. Slave Receiver mode I2CSTAT Status of the I2C-bus Status and hardware Code Application software response 0x98 0xA0 Previously addressed with General Call; DATA byte has been received; NOT ACK has been returned. A STOP condition or repeated START condition has been received while still addressed as Slave Receiver or Slave Transmitter.
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UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 Table 401. Slave Transmitter mode I2CSTAT Status of the I2C-bus Status and hardware Code 0xA8 0xB0 0xB8 0xC0 0xC8 Next action taken by I2C hardware Application software response To/From I2DAT To I2CON STA STO SI AA Own SLA+R has been Load data byte or received; ACK has been returned. Load data byte X 0 0 0 Last data byte will be transmitted and ACK bit will be received. X 0 0 1 Data byte will be transmitted; ACK will be received.
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UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 19.9.6 Miscellaneous states There are two I2STAT codes that do not correspond to a defined I2C hardware state (see Table 402). These are discussed below. 19.9.6.1 I2STAT = 0xF8 This status code indicates that no relevant information is available because the serial interrupt flag, SI, is not yet set. This occurs between other states and when the I2C block is not involved in a serial transfer. 19.9.6.
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UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 If the I2C hardware detects a repeated START condition on the I2C-bus before generating a repeated START condition itself, it will release the bus, and no interrupt request is generated. If another master frees the bus by generating a STOP condition, the I2C block will transmit a normal START condition (state 0x08), and a retry of the total serial data transfer can commence. 19.9.7.
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UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 The I2C hardware only reacts to a bus error when it is involved in a serial transfer either as a master or an addressed slave. When a bus error is detected, the I2C block immediately switches to the not addressed slave mode, releases the SDA and SCL lines, sets the interrupt flag, and loads the status register with 0x00.
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UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 19.9.8 I2C state service routines This section provides examples of operations that must be performed by various I2C state service routines. This includes: • Initialization of the I2C block after a Reset. • I2C Interrupt Service • The 26 state service routines providing support for all four I2C operating modes. 19.9.8.1 Initialization In the initialization example, the I2C block is enabled for both master and slave modes.
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UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 19.10 Software example 19.10.1 Initialization routine Example to initialize I2C Interface as a Slave and/or Master. 1. Load the I2ADR registers and I2MASK registers with values to configure the own Slave Address, enable General Call recognition if needed. 2. Enable I2C interrupt. 3. Write 0x44 to I2CONSET to set the I2EN and AA bits, enabling Slave functions. For Master only functions, write 0x40 to I2CONSET. 19.10.
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UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 1. Write 0x14 to I2CONSET to set the STO and AA bits. 2. Write 0x08 to I2CONCLR to clear the SI flag. 3. Exit 19.10.5.2 Master States State 0x08 and State 0x10 are for both Master Transmit and Master Receive modes. The R/W bit decides whether the next state is within Master Transmit mode or Master Receive mode. 19.10.5.3 State: 0x08 A START condition has been transmitted. The Slave Address + R/W bit will now be transmitted. 1.
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UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 19.10.6.2 State: 0x20 Slave Address + Write has been transmitted, NOT ACK has been received. A STOP condition will be transmitted. 1. Write 0x14 to I2CONSET to set the STO and AA bits. 2. Write 0x08 to I2CONCLR to clear the SI flag. 3. Exit 19.10.6.3 State: 0x28 Data has been transmitted, ACK has been received. If the transmitted data was the last data byte then transmit a STOP condition, otherwise transmit the next data byte. 1.
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UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 3. Exit 19.10.7.2 State: 0x48 Slave Address + Read has been transmitted, NOT ACK has been received. A STOP condition will be transmitted. 1. Write 0x14 to I2CONSET to set the STO and AA bits. 2. Write 0x08 to I2CONCLR to clear the SI flag. 3. Exit 19.10.7.3 State: 0x50 Data has been received, ACK has been returned. Data will be read from I2DAT. Additional data will be received.
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UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 19.10.8.2 State: 0x68 Arbitration has been lost in Slave Address and R/W bit as bus Master. Own Slave Address + Write has been received, ACK has been returned. Data will be received and ACK will be returned. STA is set to restart Master mode after the bus is free again. 1. Write 0x24 to I2CONSET to set the STA and AA bits. 2. Write 0x08 to I2CONCLR to clear the SI flag. 3. Set up Slave Receive mode data buffer. 4. Initialize Slave data counter. 5.
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UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 19.10.8.6 State: 0x88 Previously addressed with own Slave Address. Data has been received and NOT ACK has been returned. Received data will not be saved. Not addressed Slave mode is entered. 1. Write 0x04 to I2CONSET to set the AA bit. 2. Write 0x08 to I2CONCLR to clear the SI flag. 3. Exit 19.10.8.7 State: 0x90 Previously addressed with General Call. Data has been received, ACK has been returned. Received data will be saved.
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UM10360 NXP Semiconductors Chapter 19: LPC17xx I2C0/1/2 19.10.9.2 State: 0xB0 Arbitration lost in Slave Address and R/W bit as bus Master. Own Slave Address + Read has been received, ACK has been returned. Data will be transmitted, ACK bit will be received. STA is set to restart Master mode after the bus is free again. 1. Load I2DAT from Slave Transmit buffer with first data byte. 2. Write 0x24 to I2CONSET to set the STA and AA bits. 3. Write 0x08 to I2CONCLR to clear the SI flag. 4.
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UM10360 Chapter 20: LPC17xx I2S Rev. 2 — 19 August 2010 User manual 20.1 Basic configuration The I2S interface is configured using the following registers: 1. Power: In the PCONP register (Table 46), set bit PCI2S. Remark: On reset, the I2S interface is disabled (PCI2S = 0). 2. Clock: In PCLKSEL1 select PCLK_I2S, see Table 41. 3. Pins: Select I2S pins and their modes in PINSEL0 to PINSEL4 and PINMODE0 to PINMODE4 (see Section 8.5). 4.
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UM10360 NXP Semiconductors Chapter 20: LPC17xx I2S 20.3 Description The I2S performs serial data out via the transmit channel and serial data in via the receive channel. These support the NXP Inter IC Audio format for 8-bit, 16-bit and 32-bit audio data, both for stereo and mono modes. Configuration, data access and control is performed by a APB register set. Data streams are buffered by FIFOs with a depth of 8 words.
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UM10360 NXP Semiconductors Chapter 20: LPC17xx I2S 20.4 Pin descriptions Table 403. Pin descriptions Pin Name Type Description I2SRX_CLK Input/ Output Receive Clock. A clock signal used to synchronize the transfer of data on the receive channel. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S bus specification. I2SRX_WS Input/ Output Receive Word Select. Selects the channel from which data is to be received.
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UM10360 NXP Semiconductors Chapter 20: LPC17xx I2S 20.5 Register description Table 404 shows the registers associated with the I2S interface and a summary of their functions. Following the table are details for each register. Table 404. I2S register map Name Description Access Reset Address Value[1] I2SDAO Digital Audio Output Register. Contains control bits for the I2S transmit channel. R/W 0x87E1 0x400A 8000 I2SDAI Digital Audio Input Register. Contains control bits for the I2S receive channel.
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UM10360 NXP Semiconductors Chapter 20: LPC17xx I2S Table 405: Digital Audio Output register (I2SDAO - address 0x400A 8000) bit description Bit Symbol 2 mono 3 4 5 Value Description Reset Value When 1, data is of monaural format. When 0, the data is in stereo format. 0 stop When 1, disables accesses on FIFOs, places the transmit channel in mute mode. 0 reset When 1, asynchronously resets the transmit channel and FIFO. 0 ws_sel When 0, the interface is in master mode.
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UM10360 NXP Semiconductors Chapter 20: LPC17xx I2S Table 408: Receive FIFO register (I2RXFIFO - address 0x400A 800C) bit description Bit Symbol 31:0 I2SRXFIFO Description Reset Value 8 × 32-bit transmit FIFO. level = 0 20.5.5 Status Feedback register (I2SSTATE - 0x400A 8010) The I2SSTATE register provides status information about the I2S interface. The meaning of bits in I2SSTATE are shown in Table 409.
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UM10360 NXP Semiconductors Chapter 20: LPC17xx I2S 20.5.7 DMA Configuration Register 2 (I2SDMA2 - 0x400A 8018) The I2SDMA2 register controls the operation of DMA request 2. The function of bits in I2SDMA2 are shown in Table 405. Table 411: DMA Configuration register 2 (I2SDMA2 - address 0x400A 8018) bit description Bit Symbol Description Reset Value 0 rx_dma2_enable When 1, enables DMA1 for I2S receive. When 1, enables DMA1 for I2S 0 1 tx_dma2_enable 7:2 Unused Unused.
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UM10360 NXP Semiconductors Chapter 20: LPC17xx I2S Note: If the value of X or Y is 0, then no clock is generated. Also, the value of Y must be greater than or equal to X. Table 413: Transmit Clock Rate register (I2TXRATE - address 0x400A 8020) bit description Bit Symbol Description Reset Value 7:0 Y_divider I2S transmit MCLK rate denominator. This value is used to divide PCLK to produce the 0 transmit MCLK. Eight bits of fractional divide supports a wide range of possibilities.
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UM10360 NXP Semiconductors Chapter 20: LPC17xx I2S Table 414: Receive Clock Rate register (I2SRXRATE - address 0x400A 8024) bit description Bit Symbol Description Reset Value 7:0 Y_divider 0 I2S receive MCLK rate denominator. This value is used to divide PCLK to produce the receive MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock. 15:8 X_divider I2S receive MCLK rate numerator.
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UM10360 NXP Semiconductors Chapter 20: LPC17xx I2S Table 417: Transmit Mode Control register (I2STXMODE - 0x400A 8030) bit description Bit Symbol 1:0 TXCLKSEL Value Description Reset Value Clock source selection for the transmit bit clock divider. 00 Select the TX fractional rate divider clock output as the source 01 Reserved 10 Select the RX_MCLK signal as the TX_MCLK clock source 11 Reserved 0 2 TX4PIN Transmit 4-pin mode selection. When 1, enables 4-pin mode.
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UM10360 NXP Semiconductors Chapter 20: LPC17xx I2S 20.6 I2S transmit and receive interfaces The I2S interface can transmit and receive 8-bit, 16-bit or 32-bit stereo or mono audio information. Some details of I2S implementation are: • When the FIFO is empty, the transmit channel will repeat transmitting the same data until new data is written to the FIFO. • When mute is true, the data value 0 is transmitted. • When mono is false, two successive data words are respectively left and right data.
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UM10360 NXP Semiconductors Chapter 20: LPC17xx I2S 20.7 I2S operating modes The clocking and WS usage of the I2S interface is configurable. In addition to master and slave modes, which are independently configurable for the transmitter and the receiver, several different clock sources are possible, including variations that share the clock and/or WS between the transmitter and receiver. This last option allows using I2S with fewer pins, typically four.
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UM10360 NXP Semiconductors Chapter 20: LPC17xx I2S I2STXMODE[3] (Pin OE) I2STX_MCLK I2STX_RATE[15:8] I2STX_RATE[7:0] X I2S_PCLK I2STX_CLK I2STXBITRATE[5:0] I2S peripheral block (transmit) Y 8-bit Fractional Rate Divider TX_REF ÷2 ÷N TX bit clock (1 to 64) I2STX_SDA TX_WS ref I2STX_WS Fig 101. Typical transmitter master mode, with or without MCLK output I2STX_CLK I2STXBITRATE[5:0] RX_REF TX bit clock ÷N (1 to 64) I2S peripheral block (transmit) I2STX_SDA TX_WS ref I2STX_WS Fig 102.
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UM10360 NXP Semiconductors Chapter 20: LPC17xx I2S RX bit clock I2S peripheral block (transmit) I2STX_SDA I2STX_WS RX_WS ref Fig 106. 4-wire transmitter slave mode sharing the receiver bit clock and WS Table 420: I2S receive modes I2SDAI [5] I2SRXMODE Description [3:0] 0 0000 Typical receiver master mode. See Figure 107. The I2S receive function operates as a master. The receive clock source is the fractional rate divider. The WS used is the internally generated RX_WS.
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UM10360 NXP Semiconductors Chapter 20: LPC17xx I2S I2SRXMODE[3] (Pin OE) I2SRX_MCLK I2SRX_RATE[15:8] I2SRX_RATE[7:0] X I2S_PCLK I2SRX_CLK I2SRXBITRATE[5:0] Y 8-bit Fractional Rate Divider RX_REF ÷2 ÷N RX bit clock (1 to 64) I2S peripheral block (receive) RX_WS ref I2SRX_SDA I2SRX_WS Fig 107. Typical receiver master mode, with or without MCLK output I2SRX_CLK I2SRXBITRATE[5:0] TX_REF RX bit clock ÷N (1 to 64) I2S peripheral block (receive) RX_WS ref I2SRX_SDA I2SRX_WS Fig 108.
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UM10360 NXP Semiconductors Chapter 20: LPC17xx I2S TX bit clock I2S peripheral block (receive) I2SRX_SDA I2SRX_WS TX_WS ref Fig 112. 4-wire receiver slave mode sharing the transmitter bit clock and WS 20.8 FIFO controller Handling of data for transmission and reception is performed via the FIFO controller which can generate two DMA requests and an interrupt request. The controller consists of a set of comparators which compare FIFO levels with depth settings contained in registers.
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UM10360 NXP Semiconductors Chapter 20: LPC17xx I2S Mono 8-bit data mode 7 N+3 0 7 0 7 N+2 0 7 0 7 0 15 0 15 N+1 0 7 0 7 N 0 Stereo 8-bit data mode 7 LEFT + 1 RIGHT + 1 LEFT RIGHT 0 Mono 16-bit data mode 15 N+1 N 0 Stereo 16-bit data mode 15 LEFT RIGHT 0 Mono 32-bit data mode N 31 0 Stereo 32-bit data mode LEFT 31 RIGHT 31 0 0 N N+1 Fig 113.
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UM10360 Chapter 21: LPC17xx Timer 0/1/2/3 Rev. 2 — 19 August 2010 User manual 21.1 Basic configuration The Timer 0, 1, 2, and 3 peripherals are configured using the following registers: 1. Power: In the PCONP register (Table 46), set bits PCTIM0/1/2/3. Remark: On reset, Timer0/1 are enabled (PCTIM0/1 = 1), and Timer2/3 are disabled (PCTIM2/3 = 0). 2. Peripheral clock: In the PCLKSEL0 register (Table 40), select PCLK_TIMER0/1; in the PCLKSEL1 register (Table 41), select PCLK_TIMER2/3. 3.
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UM10360 NXP Semiconductors Chapter 21: LPC17xx Timer 0/1/2/3 21.3 Applications • Interval Timer for counting internal events. • Pulse Width Demodulator via Capture inputs. • Free running timer. 21.4 Description The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an externally-supplied clock, and can optionally generate interrupts or perform other actions at specified timer values, based on four match registers.
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UM10360 NXP Semiconductors Chapter 21: LPC17xx Timer 0/1/2/3 21.6 Register description Each Timer/Counter contains the registers shown in Table 425 ("Reset Value" refers to the data stored in used bits only; it does not include reserved bits content). More detailed descriptions follow. Table 425. TIMER/COUNTER0-3 register map Generic Description Name Access Reset TIMERn Register/ Value[1] Name & Address IR Interrupt Register. The IR can be written to clear interrupts.
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UM10360 NXP Semiconductors Chapter 21: LPC17xx Timer 0/1/2/3 Table 425. TIMER/COUNTER0-3 register map Generic Description Name Access Reset TIMERn Register/ Value[1] Name & Address CR0 Capture Register 0. CR0 is loaded with the value of TC when there RO is an event on the CAPn.0(CAP0.0 or CAP1.0 respectively) input. 0 T0CR0 - 0x4000 402C T1CR0 - 0x4000 802C T2CR0 - 0x4009 002C T3CR0 - 0x4009 402C CR1 Capture Register 1. See CR0 description.
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UM10360 NXP Semiconductors Chapter 21: LPC17xx Timer 0/1/2/3 Table 427. Timer Control Register (TCR, TIMERn: TnTCR - addresses 0x4000 4004, 0x4000 8004, 0x4009 0004, 0x4009 4004) bit description Bit Symbol Description Reset Value 0 Counter Enable When one, the Timer Counter and Prescale Counter are enabled for counting. When 1, the counters are disabled. 0 1 Counter Reset When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK.
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UM10360 NXP Semiconductors Chapter 21: LPC17xx Timer 0/1/2/3 Table 428. Count Control Register (T[0/1/2/3]CTCR - addresses 0x4000 4070, 0x4000 8070, 0x4009 0070, 0x4009 4070) bit description Bit Symbol 3:2 Count Input Select Value Description Reset Value When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. 00 CAPn.0 for TIMERn 01 CAPn.
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UM10360 NXP Semiconductors Chapter 21: LPC17xx Timer 0/1/2/3 21.6.7 Match Registers (MR0 - MR3) The Match register values are continuously compared to the Timer Counter value. When the two values are equal, actions can be triggered automatically. The action possibilities are to generate an interrupt, reset the Timer Counter, or stop the timer. Actions are controlled by the settings in the MCR register. 21.6.
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UM10360 NXP Semiconductors Chapter 21: LPC17xx Timer 0/1/2/3 21.6.9 Capture Registers (CR0 - CR1) Each Capture register is associated with a device pin and may be loaded with the Timer Counter value when a specified event occurs on that pin. The settings in the Capture Control Register register determine whether the capture function is enabled, and whether a capture event happens on the rising edge of the associated pin, the falling edge, or on both edges. 21.6.
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UM10360 NXP Semiconductors Chapter 21: LPC17xx Timer 0/1/2/3 Match events for Match 0 and Match 1 in each timer can cause a DMA request, see Section 21.6.12. Table 431. External Match Register (T[0/1/2/3]EMR - addresses 0x4000 403C, 0x4000 803C, 0x4009 003C, 0x4009 403C) bit description Bit Symbol Description Reset Value 0 EM0 External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register.
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UM10360 NXP Semiconductors Chapter 21: LPC17xx Timer 0/1/2/3 When a timer is initially set up to generate a DMA request, the request may already be asserted before a match condition occurs. An initial DMA request may be avoided by having software write a one to the interrupt flag location, as if clearing a timer interrupt. See Section 21.6.1. A DMA request will be cleared automatically when it is acted upon by the GPDMA controller.
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UM10360 NXP Semiconductors Chapter 21: LPC17xx Timer 0/1/2/3 21.8 Architecture The block diagram for TIMER/COUNTER0 and TIMER/COUNTER1 is shown in Figure 116.
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UM10360 Chapter 22: LPC17xx Repetitive Interrupt Timer (RIT) Rev. 2 — 19 August 2010 User manual 22.1 Features • 32-bit counter running from PCLK. Counter can be free-running, or be reset by a generated interrupt. • 32-bit compare value. • 32-bit compare mask. An interrupt is generated when the counter value equals the compare value, after masking. This allows for combinations not possible with a simple compare. 22.
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UM10360 NXP Semiconductors Chapter 22: LPC17xx Repetitive Interrupt Timer (RIT) 22.3.3 RI Control register (RICTRL - 0x400B 0008) Table 436. RI Control register (RICTRL - address 0x400B 0008) bit description Bit Symbol 0 RITINT Value Description Reset value Interrupt flag 0 1 This bit is set to 1 by hardware whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. 0 The counter value does not equal the masked compare value.
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UM10360 NXP Semiconductors Chapter 22: LPC17xx Repetitive Interrupt Timer (RIT) Counting can be halted in software by writing a ‘0’ to the Enable_Timer bit - RICTRL(2). Counting will also be halted when the processor is halted for debugging provided the Enable_Break bit – RICTRL(1) is set. Both the Enable_Timer and Enable_Break bits are set on reset. The interrupt flag can be cleared in software by writing a ‘1’ to the Interrupt bit – RICTRL(0).
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UM10360 Chapter 23: LPC17xx System Tick Timer Rev. 2 — 19 August 2010 User manual 23.1 Basic configuration The System Tick Timer is configured using the following registers: 1. Clock Source: Select either the internal CCLK or external STCLK (P3.26) clock as the source in the STCTRL register. 2. Pins: If STCLK (P3.26) was selected as clock source enable the STCLK pin function in the PINMODE register (Section 8.5). 3.
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UM10360 NXP Semiconductors Chapter 23: LPC17xx System Tick Timer STCALIB STRELOAD load data STCURR 24-bit down counter cclk STCLK pin private peripheral bus clock D Q under- count flow enable load ENABLE CLKSOURCE STCTRL COUNTFLAG TICKINT System Tick interrupt Fig 118. System Tick Timer block diagram 23.5 Register description Table 438.
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UM10360 NXP Semiconductors Chapter 23: LPC17xx System Tick Timer Table 439. System Timer Control and status register (STCTRL - 0xE000 E010) bit description Bit Symbol Description Reset value 15:3 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 16 COUNTFLAG System Tick counter flag. This flag is set when the System Tick counter counts down to 0, and is cleared by reading this register.
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UM10360 NXP Semiconductors Chapter 23: LPC17xx System Tick Timer Table 442. System Timer Calibration value register (STCALIB - 0xE000 E01C) bit description Bit Symbol Value Description Reset value 23:0 TENMS Reload value to get a 10 millisecond System Tick underflow rate when running 0x0F 423F at 100 MHz. This value initialized at reset with a factory supplied value selected for the LPC17xx.
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UM10360 NXP Semiconductors Chapter 23: LPC17xx System Tick Timer 23.6 Example timer calculations The following examples illustrate selecting System Tick Timer values for different system configurations. All of the examples calculate an interrupt interval of 10 milliseconds, as the System Tick Timer is intended to be used. Example 1) This example is for the System Tick Timer running from the CPU clock (cclk), which is 100 MHz. STCTRL = 7.
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UM10360 Chapter 24: LPC17xx Pulse Width Modulator (PWM) Rev. 2 — 19 August 2010 User manual 24.1 Basic configuration The PWM is configured using the following registers: 1. Power: In the PCONP register (Table 46), set bit PCPWM1. Remark: On reset, the PWM is enabled (PCPWM1 = 1). 2. Peripheral clock: In the PCLKSEL0 register (Table 40), select PCLK_PWM1. 3. Pins: Select PWM pins through the PINSEL registers. Select pin modes for port pins with PWM1 functions through the PINMODE registers (Section 8.5). 4.
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UM10360 NXP Semiconductors Chapter 24: LPC17xx Pulse Width Modulator (PWM) 24.3 Description The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC17xx. The Timer is designed to count cycles of the peripheral clock (PCLK) and optionally generate interrupts or perform other actions when specified timer values occur, based on seven match registers.
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UM10360 NXP Semiconductors Chapter 24: LPC17xx Pulse Width Modulator (PWM) MATCH REGISTER 0 SHADOW REGISTER 0 LOAD ENABLE MATCH REGISTER 1 SHADOW REGISTER 1 LOAD ENABLE MATCH REGISTER 2 SHADOW REGISTER 2 LOAD ENABLE MATCH REGISTER 3 SHADOW REGISTER 3 LOAD ENABLE MATCH REGISTER 4 Match 0 SHADOW REGISTER 4 LOAD ENABLE MATCH REGISTER 5 SHADOW REGISTER 5 LOAD ENABLE MATCH REGISTER 6 S Match 1 SHADOW REGISTER 6 LOAD ENABLE Q R EN PWM1 PWMENA1 PWMSEL2 S MUX Q PWM2 PWMENA2 Match 2 R EN
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UM10360 NXP Semiconductors Chapter 24: LPC17xx Pulse Width Modulator (PWM) 24.4 Sample waveform with rules for single and double edge control A sample of how PWM values relate to waveform outputs is shown in Figure 120. PWM output logic is shown in Figure 119 that allows selection of either single or double edge controlled PWM outputs via the muxes controlled by the PWMSELn bits. The match register selections for various PWM outputs is shown in Table 443.
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UM10360 NXP Semiconductors Chapter 24: LPC17xx Pulse Width Modulator (PWM) 24.4.1 Rules for Single Edge Controlled PWM Outputs 1. All single edge controlled PWM outputs go high at the beginning of a PWM cycle unless their match value is equal to 0. 2. Each PWM output will go low when its match value is reached. If no match occurs (i.e. the match value is greater than the PWM rate), the PWM output remains continuously high. 24.4.
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UM10360 NXP Semiconductors Chapter 24: LPC17xx Pulse Width Modulator (PWM) 24.6 Register description The PWM1 function includes registers as shown in Table 445 below. Table 445. PWM1 register map Generic Description Name IR TCR Access Reset PWMn Register Value[1] Name & Address Interrupt Register. The IR can be written to clear interrupts. The IR can be R/W read to identify which of eight possible interrupt sources are pending. 0 Timer Control Register.
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UM10360 NXP Semiconductors Chapter 24: LPC17xx Pulse Width Modulator (PWM) Table 445. PWM1 register map Generic Description Name MR4 Access Reset PWMn Register Value[1] Name & Address Match Register 4. MR4 can be enabled in the MCR to reset the TC, stop R/W both the TC and PC, and/or generate an interrupt when it matches the TC. In addition, a match between this value and the TC clears PWM4 in either edge mode, and sets PWM5 if it’s in double-edge mode. 0 Match Register 5.
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UM10360 NXP Semiconductors Chapter 24: LPC17xx Pulse Width Modulator (PWM) 24.6.2 PWM Timer Control Register (PWM1TCR 0x4001 8004) The PWM Timer Control Register (PWMTCR) is used to control the operation of the PWM Timer Counter. The function of each of the bits is shown in Table 447. Table 447. PWM Timer Control Register (PWM1TCR address 0x4001 8004) bit description Bit Symbol Value Description Reset Value 0 Counter Enable 1 The PWM Timer Counter and PWM Prescale Counter are enabled for counting.
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UM10360 NXP Semiconductors Chapter 24: LPC17xx Pulse Width Modulator (PWM) 24.6.4 PWM Match Control Register (PWM1MCR - 0x4001 8014) The PWM Match Control Registers are used to control what operations are performed when one of the PWM Match Registers matches the PWM Timer Counter. The function of each of the bits is shown in Table 449. Table 449: Match Control Register (PWM1MCR - address 0x4001 8014) bit description Bit Symbol Value Description 0 PWMMR0I 1 0 This interrupt is disabled.
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UM10360 NXP Semiconductors Chapter 24: LPC17xx Pulse Width Modulator (PWM) Table 449: Match Control Register (PWM1MCR - address 0x4001 8014) bit description Bit Symbol Value Description Reset Value 14 PWMMR4S 1 Stop on PWMMR4: the PWMTC and PWMPC will be stopped and PWMTCR[0] will be 0 set to 0 if PWMMR4 matches the PWMTC. 0 This feature is disabled 15 PWMMR5I 1 Interrupt on PWMMR5: An interrupt is generated when PWMMR5 matches the value in the PWMTC. 0 This interrupt is disabled.
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UM10360 NXP Semiconductors Chapter 24: LPC17xx Pulse Width Modulator (PWM) Table 450: PWM Capture Control Register (PWM1CCR - address 0x4001 8028) bit description Bit Symbol Value Description Reset Value 3 Capture on CAPn.1rising edge 0 This feature is disabled. 0 1 A synchronously sampled rising edge on the CAPn.1 input will cause CR1 to be loaded with the contents of the TC. Capture on CAPn.1falling edge 0 This feature is disabled. 1 A synchronously sampled falling edge on CAPn.
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UM10360 NXP Semiconductors Chapter 24: LPC17xx Pulse Width Modulator (PWM) Table 451: PWM Control Register (PWM1PCR - address 0x4001 804C) bit description Bit Symbol Value Description Reset Value 14 PWMENA6 1 0 The PWM6 output enabled. 0 The PWM6 output disabled. 31:15 Unused Unused, always zero. NA 24.6.7 PWM Latch Enable Register (PWM1LER - 0x4001 8050) The PWM Latch Enable Registers are used to control the update of the PWM Match registers when they are used for PWM generation.
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UM10360 NXP Semiconductors Chapter 24: LPC17xx Pulse Width Modulator (PWM) Table 452: PWM Latch Enable Register (PWM1LER - address 0x4001 8050) bit description Bit Symbol Description Reset Value 4 Enable PWM Match 4 Latch Writing a one to this bit allows the last value written to the PWM Match 4 register to be become effective when the timer is next reset by a PWM Match event. See Section 24.6.4 “PWM Match Control Register (PWM1MCR - 0x4001 8014)”.
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UM10360 Chapter 25: LPC17xx Motor control PWM Rev. 2 — 19 August 2010 User manual 25.1 Introduction The Motor Control PWM (MCPWM) is optimized for three-phase AC and DC motor control applications, but can be used in many other applications that need timing, counting, capture, and comparison. 25.
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UM10360 NXP Semiconductors Chapter 25: LPC17xx Motor control PWM 25.
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UM10360 NXP Semiconductors Chapter 25: LPC17xx Motor control PWM 25.5 Configuring other modules for MCPWM use Configure the following registers in other modules before using the Motor Control PWM: 1. Power: in the PCONP register (Table 46), set bit PCMCPWM. Remark: On reset the MCPWM is disabled (PCMCPWM = 0). 2. Peripheral clock: in the PCLKSEL1 register (Table 40) select PCLK_MCPWM. 3. Pins: select MCPWM functions through the PINSEL registers.
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UM10360 NXP Semiconductors Chapter 25: LPC17xx Motor control PWM 25.7 Register description “Control” registers and “interrupt” registers have separate read, set, and clear addresses. Reading such a register’s read address(e.g. MCCON) yields the state of the register bits. Writing ones to the set address (e.g. MCCON_SET) sets register bit(s), and writing ones to the clear address (e.g. MCCON_CLR) clears register bit(s).
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UM10360 NXP Semiconductors Chapter 25: LPC17xx Motor control PWM 25.7.1 MCPWM Control register 25.7.1.1 MCPWM Control read address (MCCON - 0x400B 8000) The MCCON register controls the operation of all channels of the PWM. This address is read-only, but the underlying register can be modified by writing to addresses MCCON_SET and MCCON_CLR. Table 455. MCPWM Control read address (MCCON - 0x400B 8000) bit description Bit Symbol 0 RUN0 1 2 3 Value Description Stops/starts timer channel 0. 0 Stop.
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UM10360 NXP Semiconductors Chapter 25: LPC17xx Motor control PWM Table 455. MCPWM Control read address (MCCON - 0x400B 8000) bit description Bit Symbol Value Description Reset value 15:13 - - Reserved. 0 16 RUN2 Stops/starts timer channel 2. 0 0 Stop. 1 Run. 17 18 CENTER2 Edge/center aligned operation for channel 2. 0 Edge-aligned. 1 Center-aligned. POLA2 Selects polarity of the MCOA2 and MCOB2 pins.
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UM10360 NXP Semiconductors Chapter 25: LPC17xx Motor control PWM 25.7.1.3 MCPWM Control clear address (MCCON_CLR - 0x400B 8008) Writing ones to this write-only address clears the corresponding bits in MCCON. Table 457. MCPWM Control clear address (MCCON_CLR - 0x400B 8008) bit description Bit Description 31:0 Writing ones to this address clears the corresponding bits in the MCCON register. See Table 455. 25.7.2 MCPWM Capture Control register 25.7.2.
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UM10360 NXP Semiconductors Chapter 25: LPC17xx Motor control PWM 25.7.2.2 MCPWM Capture Control set address (MCCAPCON_SET - 0x400B 8010) Writing ones to this write-only address sets the corresponding bits in MCCAPCON. Table 459. MCPWM Capture Control set address (MCCAPCON_SET - 0x400B 8010) bit description Bit Description 31:0 Writing ones to this address sets the corresponding bits in the MCCAPCON register. See Table 458. 25.7.2.
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UM10360 NXP Semiconductors Chapter 25: LPC17xx Motor control PWM 25.7.3.2 MCPWM Interrupt Enable set address (MCINTEN_SET - 0x400B 8054) Writing ones to this write-only address sets the corresponding bits in MCINTEN, thus enabling interrupts. Table 464. PWM interrupt enable set register (MCINTEN_SET - address 0x400B 8054) bit description Bit Description 31:0 Writing ones to this address sets the corresponding bits in MCINTEN, thus enabling interrupts. See Table 462. 25.7.3.
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UM10360 NXP Semiconductors Chapter 25: LPC17xx Motor control PWM Table 468. MCPWM Interrupt Flags clear address (PWMINTF_CLR - 0x400B 8070) bit description Bit Description 31:0 Writing one(s) to this write-only address sets the corresponding bit(s) in the MCINTF register, thus clearing the corresponding interrupt request(s). See Table 462. 25.7.4 MCPWM Count Control register 25.7.4.
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UM10360 NXP Semiconductors Chapter 25: LPC17xx Motor control PWM Table 469. MCPWM Count Control read address (MCCNTCON - 0x400B 805C) bit description Bit Symbol Value Description Reset Value 13 TC2MCI0_FE 1 0 0 A falling edge on MCI0 does not affect counter 2. 14 TC2MCI1_RE 1 If MODE2 is 1, counter 2 advances on a rising edge on MCI1. 0 A rising edge on MCI1 does not affect counter 2. If MODE2 is 1, counter 2 advances on a falling edge on MCI1.
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UM10360 NXP Semiconductors Chapter 25: LPC17xx Motor control PWM Table 472. MCPWM Timer/Counter 0-2 registers (MCTC0-2 - 0x400B 8018, 0x400B 801C, 0x400B 8020) bit description Bit Symbol Description Reset value 31:0 MCTC0/1/2 Timer/Counter values for channels 0, 1, 2. 0 25.7.6 MCPWM Limit 0-2 registers (MCLIM0-2 - 0x400B 8024, 0x400B 8028, 0x400B 802C) These registers hold the limiting values for timer/counters 0-2.
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UM10360 NXP Semiconductors Chapter 25: LPC17xx Motor control PWM 25.7.7 MCPWM Match 0-2 registers (MCMAT0-2 - 0x400B 8030, 0x400B 8034, 0x400B 8038) These registers also have “write” and “operating” versions as described above for the Limit registers, and the operating registers are also compared to the channels’ TCs. See 25.7.6 above for details of reading and writing both Limit and Match registers. The Match and Limit registers control the MCO0-2 outputs.
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UM10360 NXP Semiconductors Chapter 25: LPC17xx Motor control PWM 25.7.8 MCPWM Dead-time register (MCDT - 0x400B 803C) This register holds the dead-time values for the three channels. If a channel’s DTE bit in MCCON is 1 to enable its dead-time counter, the counter counts down from this value whenever one its channel’s outputs changes from “active” to “passive” state. When the dead-time counter reaches 0, the channel changes its other output from “passive” to “active” state.
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UM10360 NXP Semiconductors Chapter 25: LPC17xx Motor control PWM 25.7.10 MCPWM Capture Registers 25.7.10.1 MCPWM Capture read addresses (MCCAP0-2 - 0x400B 8044, 0x400B 8048, 0x400B 804C) The MCCAPCON register (Table 458) allows software to select any edge(s) on any of the MCI0-2 inputs as a capture event for each channel. When a channel’s capture event occurs, the current TC value for that channel is stored in its read-only Capture register.
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UM10360 NXP Semiconductors Chapter 25: LPC17xx Motor control PWM 25.8 PWM operation 25.8.1 Pulse-width modulation Each channel of the MCPWM has two outputs, A and B, that can drive a pair of transistors to switch a controlled point between two power rails.
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UM10360 NXP Semiconductors Chapter 25: LPC17xx Motor control PWM active passive active passive passive active passive active MCOB POLA = 0 MCOA MAT 0 LIM 0 MAT LIM Fig 123. Center-aligned PWM waveform without dead time, POLA = 0 Dead-time counter When the a channel’s DTE bit is set in MCCON, the dead-time counter delays the passive-to-active transitions of both MCO outputs.
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UM10360 NXP Semiconductors Chapter 25: LPC17xx Motor control PWM active active passive passive MCOB DT active active passive passive POLA = 0 MCOA DT 0 MAT LIM DT MAT 0 LIM Fig 125. Center-aligned waveform with dead time, POLA = 0 25.8.2 Shadow registers and simultaneous updates The Limit, Match, and Commutation Pattern registers (MCLIM, MCMAT, and MCCP) are implemented as register pairs, each consisting of a write register and an operational register.
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UM10360 NXP Semiconductors Chapter 25: LPC17xx Motor control PWM If a channel’s HNF bit in the MCCAPCON register is set to enable “noise filtering”, a selected edge on an MCI pin starts the dead-time counter for that channel, and the capture event actions described below are delayed until the dead-time counter reaches 0. This function is targeted specifically for performing three-phase brushless DC motor control with Hall sensors.
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UM10360 NXP Semiconductors Chapter 25: LPC17xx Motor control PWM MCOB2 CCPB2 = 1, on-state MCOA2 CCPA2 = 1, on-state MCOB1 CCPB1 = 0, off-state MCOA1 CCPA1 = 1, on-state MCOB0 CCPB0 = 0, off-state CCPA0 = 1, on-state MCOA0 POLA0 = 0, INVBDC = 0 Fig 126. Three-phase DC mode sample waveforms 25.8.7 Three phase AC mode The three-phase AC-mode is selected by setting the ACMODE bit in the MCCON register.
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UM10360 NXP Semiconductors Chapter 25: LPC17xx Motor control PWM MCOB2 POLA2 = 0 MCOA2 MAT2 MAT2 MCOB1 POLA1 = 0 MCOA1 MAT1 MAT1 MCOB0 POLA0 = 0 MCOA0 0 MAT0 LIM0 timer reset LIM0 timer reset Fig 127. Three-phase AC mode sample waveforms, edge aligned PWM mode 25.8.8 Interrupts The MCPWM includes 10 possible interrupt sources: • When any channel’s TC matches its Match register. • When any channel’s TC matches its Limit register.
PAGE 543
UM10360 Chapter 26: LPC17xx Quadrature Encoder Interface (QEI) Rev. 2 — 19 August 2010 User manual 26.1 Basic configuration The QEI is configured using the following registers: 1. Power: In the PCONP register (Table 46), set bit PCQEI. Remark: On reset, the QEI is disabled (PCQEI = 0). 2. Peripheral clock: In the PCLKSEL0 register (Table 40), select PCLK_QEI. 3. Pins: Select QEI pins through the PINSEL registers. Select pin modes for port pins with QEI functions through the PINMODE registers (Section 8.
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UM10360 NXP Semiconductors Chapter 26: LPC17xx Quadrature Encoder Interface (QEI) VELOCITY TIMER velocity interrupt (TIM_Int) VELOCITY RELOAD VELOCITY COMPARE RST index Ph A Ph B PCLK low velocity interrupt (LVEL_Int) VELOCITY CAPTURE RST DIGITAL FILTER QUAD DECODER CLK VELOCITY COUNTER encoder clock interrupt (ENCLK_Int) POSITION COMPARE 0 CLK DIR INX position 0 interrupt (POS0_Int) POSITION COUNTER POSITION COMPARE 1 position 1 interrupt (POS1_Int) direction interrupt (DIR_Int) INDEX C
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UM10360 NXP Semiconductors Chapter 26: LPC17xx Quadrature Encoder Interface (QEI) 26.4 Functional description The QEI module interprets the two-bit gray code produced by a quadrature encoder wheel to integrate position over time and determine direction of rotation. In addition, it can capture the velocity of the encoder wheel. 26.4.1 Input signals The QEI module supports two modes of signal operation: quadrature phase mode and clock/direction mode.
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UM10360 NXP Semiconductors Chapter 26: LPC17xx Quadrature Encoder Interface (QEI) Table 481. Encoder direction DIR bit DIRINV bit direction 0 0 forward 1 0 reverse 0 1 reverse 1 1 forward Figure 129 shows how quadrature encoder signals equate to direction and count. PhA PhB direction position -1 -1 -1 -1 -1 -1 -1 -1 -1 +1 +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 Fig 129.Quadrature Encoder Basic Operation 26.4.1.
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UM10360 NXP Semiconductors Chapter 26: LPC17xx Quadrature Encoder Interface (QEI) number of edges counted in a given time period is directly proportional to the velocity of the encoder. Setting the reset velocity bit (RESV) has the same effect as an overflow of the velocity timer, except that the setting the RESV bit will not generate a velocity interrupt.
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UM10360 NXP Semiconductors Chapter 26: LPC17xx Quadrature Encoder Interface (QEI) 26.5 Pin description Table 482. QEI pin description Pin name I/O Description MCI0 [1] I Used as the Phase A (PhA) input to the Quadrature Encoder Interface. MCI1 [1] I Used as the Phase B (PhB) input to the Quadrature Encoder Interface. MCI2 [1] I Used as the Index (IDX) input to the Quadrature Encoder Interface.
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UM10360 NXP Semiconductors Chapter 26: LPC17xx Quadrature Encoder Interface (QEI) 26.6 Register description 26.6.1 Register summary Table 483.
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UM10360 NXP Semiconductors Chapter 26: LPC17xx Quadrature Encoder Interface (QEI) 26.6.2 Control registers 26.6.2.1 QEI Control register (QEICON - 0x400B C000) This register contains bits which control the operation of the position and velocity counters of the QEI module. Table 484: QEI Control register (QEICON - address 0x400B C000) bit description Bit Symbol Description Reset value 0 RESP Reset position counter. When set = 1, resets the position counter to all zeros.
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UM10360 NXP Semiconductors Chapter 26: LPC17xx Quadrature Encoder Interface (QEI) 26.6.3 Position, index and timer registers 26.6.3.1 QEI Position register (QEIPOS - 0x400B C00C) This register contains the current value of the encoder position. Increments or decrements when encoder counts occur, depending on the direction of rotation. Table 487: QEI Position register (QEIPOS - address 0x400B C00C) bit description Bit Symbol Description Reset value 31:0 - Current position value. 0 26.6.3.
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UM10360 NXP Semiconductors Chapter 26: LPC17xx Quadrature Encoder Interface (QEI) 26.6.3.5 QEI Position Compare register 2 (CMPOS2 - 0x400B C01C) This register contains a position compare value. This value is compared against the current value of the position register. Interrupts can be enabled to interrupt when the compare value is equal to the current value of the position register.
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UM10360 NXP Semiconductors Chapter 26: LPC17xx Quadrature Encoder Interface (QEI) 26.6.3.10 QEI Velocity register (QEIVEL - 0x400B C030) This register contains the running count of velocity pulses for the current time period. When the velocity timer (QEITIME) overflows the contents of this register is captured in the velocity capture register (QEICAP). After capture, this register is set to zero. This register is also reset when the velocity reset bit (RESV) is asserted.
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UM10360 NXP Semiconductors Chapter 26: LPC17xx Quadrature Encoder Interface (QEI) 26.6.4 Interrupt registers 26.6.4.1 QEI Interrupt Status register (QEIINTSTAT) This register provides the status of the encoder interface and the current set of interrupt sources that are asserted to the controller. Bits set to 1 indicate the latched events that have occurred; a zero bit indicates that the event in question has not occurred. Writing a 0 to a bit position clears the corresponding interrupt.
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UM10360 NXP Semiconductors Chapter 26: LPC17xx Quadrature Encoder Interface (QEI) Table 501: QEI Interrupt Set register (QEISET - address 0x400B CFEC) bit description Bit Symbol Description Reset value 10 POS0REV_Int Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set 0 and the REV_Int is set. 11 POS1REV_Int Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set 0 and the REV_Int is set.
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UM10360 NXP Semiconductors Chapter 26: LPC17xx Quadrature Encoder Interface (QEI) Table 503: QEI Interrupt Enable register (QEIIE - address 0x400B CFE4) bit description Bit Symbol Description Reset value 4 ERR_Int Indicates that an encoder phase error was detected. 0 5 ENCLK_Int Indicates that and encoder clock pulse was detected. 0 6 POS0_Int Indicates that the position 0 compare value is equal to the current position.
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UM10360 NXP Semiconductors Chapter 26: LPC17xx Quadrature Encoder Interface (QEI) 26.6.4.6 QEI Interrupt Enable Clear register (QEIIEC - 0x400B CFD8) Writing a 1 to a bit in this register clears the corresponding bit in the QEI Interrupt Enable register (QEIIE). Table 505: QEI Interrupt Enable Clear register (QEIIEC - address 0x400B CFD8) bit description Bit Symbol Description Reset value 0 INX_EN Indicates that an index pulse was detected.
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UM10360 Chapter 27: LPC17xx Real-Time Clock (RTC) and backup registers Rev. 2 — 19 August 2010 User manual 27.1 Basic configuration The RTC is configured using the following registers: 1. Power: In the PCONP register (Table 46), set bits PCRTC. Remark: On reset, the RTC is enabled. See Section 27.7 for power saving options. 2. Clock: The RTC uses the 1 Hz clock output from the RTC oscillator as the only clock source. The peripheral clock rate for accessing registers is CCLK/8. 3.
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UM10360 NXP Semiconductors Chapter 27: LPC17xx Real-Time Clock (RTC) and backup registers 27.4 Architecture VDD(REG)(3v3) pin to main regulator RTC power domain Ultra-low power regulator Power selector VBAT pin Backup Registers RTC power RTCX1 Ultra-low power oscillator 1 Hz clock Real Time Clock Functional Block RTC Alarm & Interrupt RTCX2 Fig 130.
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UM10360 NXP Semiconductors Chapter 27: LPC17xx Real-Time Clock (RTC) and backup registers 27.5 Pin description Table 506. RTC pin description Name Type Description RTCX1 I Input to the RTC oscillator circuit. RTCX2 O Output from the RTC oscillator circuit. Remark: If the RTC is not used, the RTCX1/2 pins can be left floating. VBAT I RTC power supply: Typically connected to an external 3V battery. If this pin is not powered, the RTC is still powered internally if VDD(REG)(3V3) is present. 27.
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UM10360 NXP Semiconductors Chapter 27: LPC17xx Real-Time Clock (RTC) and backup registers Table 507. Real-Time Clock register map Name Description Access Reset Value[1] Address Miscellaneous registers (see Section 27.6.
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UM10360 NXP Semiconductors Chapter 27: LPC17xx Real-Time Clock (RTC) and backup registers 27.6.1 RTC interrupts Interrupt generation is controlled through the Interrupt Location Register (ILR), Counter Increment Interrupt Register (CIIR), the alarm registers, and the Alarm Mask Register (AMR). Interrupts are generated only by the transition into the interrupt state. The ILR separately enables CIIR and AMR interrupts. Each bit in CIIR corresponds to one of the time counters.
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UM10360 NXP Semiconductors Chapter 27: LPC17xx Real-Time Clock (RTC) and backup registers Table 509. Clock Control Register (CCR - address 0x4002 4008) bit description Bit Symbol 1 CTCRST Value Description Reset value CTC Reset. 0 1 When one, the elements in the internal oscillator divider are reset, and remain reset until CCR[1] is changed to zero. This is the divider that generates the 1 Hz clock from the 32.768 kHz crystal. The state of the divider is not visible to software. 0 No effect.
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UM10360 NXP Semiconductors Chapter 27: LPC17xx Real-Time Clock (RTC) and backup registers Table 511. Alarm Mask Register (AMR - address 0x4002 4010) bit description Bit Symbol Description Reset value 0 AMRSEC When 1, the Second value is not compared for the alarm. 0 1 AMRMIN When 1, the Minutes value is not compared for the alarm. 0 2 AMRHOUR When 1, the Hour value is not compared for the alarm. 0 3 AMRDOM When 1, the Day of Month value is not compared for the alarm.
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UM10360 NXP Semiconductors Chapter 27: LPC17xx Real-Time Clock (RTC) and backup registers 27.6.3 Consolidated time registers The values of the Time Counters can optionally be read in a consolidated format which allows the programmer to read all time counters with only three read operations. The various registers are packed into 32-bit values as shown in Table 514, Table 515, and Table 516. The least significant bit of each register is read back at bit 0, 8, 16, or 24.
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UM10360 NXP Semiconductors Chapter 27: LPC17xx Real-Time Clock (RTC) and backup registers Table 516. Consolidated Time register 2 (CTIME2 - address 0x4002 401C) bit description Bit Symbol Description Reset value 11:0 Day of Year Day of year value in the range of 1 to 365 (366 for leap years). NC 31:12 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 27.6.
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UM10360 NXP Semiconductors Chapter 27: LPC17xx Real-Time Clock (RTC) and backup registers Table 519. Calibration register (CALIBRATION - address 0x4002 4040) bit description Bit Symbol Value Description 16:0 CALVAL - If enabled, the calibration counter counts up to this value. The maximum value is 131, NC 072 corresponding to about 36.4 hours. Calibration is disabled if CALVAL = 0. 17 CALDIR 31:12 Reset value Calibration direction NC 1 Backward calibration.
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UM10360 NXP Semiconductors Chapter 27: LPC17xx Real-Time Clock (RTC) and backup registers 27.6.6 General purpose registers 27.6.6.1 General purpose registers 0 to 4 (GPREG0 to GPREG4 - addresses 0x4002 4044 to 0x4002 4054) These registers can be used to store important information when the main power supply is off. The value in these registers is not affected by chip reset. Table 520.
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UM10360 Chapter 28: LPC17xx Watchdog Timer (WDT) Rev. 2 — 19 August 2010 User manual 28.1 Features • Internally resets chip if not periodically reloaded. • Debug mode. • Enabled by software but requires a hardware reset or a Watchdog reset/interrupt to be disabled. • • • • Incorrect/Incomplete feed sequence causes reset/interrupt if enabled. Flag to indicate Watchdog reset. Programmable 32-bit timer with internal pre-scaler.
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UM10360 NXP Semiconductors Chapter 28: LPC17xx Watchdog Timer (WDT) 28.3 Description The Watchdog consists of a divide by 4 fixed pre-scaler and a 32-bit counter. The clock is fed to the timer via a pre-scaler. The timer decrements when clocked. The minimum value from which the counter decrements is 0xFF. Setting a value lower than 0xFF causes 0xFF to be loaded in the counter.
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UM10360 NXP Semiconductors Chapter 28: LPC17xx Watchdog Timer (WDT) 28.4.1 Watchdog Mode register (WDMOD - 0x4000 0000) The WDMOD register controls the operation of the Watchdog as per the combination of WDEN and RESET bits. Note that a watchdog feed must be performed before any changes to the WDMOD register take effect. Table 523: Watchdog Mode register (WDMOD - address 0x4000 0000) bit description Bit Symbol Description Reset Value 0 WDEN WDEN Watchdog enable bit (set-only).
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UM10360 NXP Semiconductors Chapter 28: LPC17xx Watchdog Timer (WDT) 28.4.2 Watchdog Timer Constant register (WDTC - 0x4000 0004) The WDTC register determines the time-out value. Every time a feed sequence occurs the WDTC content is reloaded in to the Watchdog timer. It’s a 32-bit register with 8 LSB set to 1 on reset. Writing values below 0xFF will cause 0x0000 00FF to be loaded to the WDTC. Thus the minimum time-out interval is TWDCLK × 256 × 4.
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UM10360 NXP Semiconductors Chapter 28: LPC17xx Watchdog Timer (WDT) Table 528: Watchdog Timer Clock Source Selection register (WDCLKSEL - address 0x4000 0010) bit description Bit Symbol 1:0 WDSEL Value Description Reset Value These bits select the clock source for the Watchdog timer as described below. 0 Warning: Improper setting of this value may result in incorrect operation of the Watchdog timer, which could adversely affect system operation.
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UM10360 Chapter 29: LPC17xx Analog-to-Digital Converter (ADC) Rev. 2 — 19 August 2010 User manual 29.1 Basic configuration The ADC is configured using the following registers: 1. Power: In the PCONP register (Table 46), set the PCADC bit. Remark: On reset, the ADC is disabled. To enable the ADC, first set the PCADC bit, and then enable the ADC in the AD0CR register (bit PDN Table 531). To disable the ADC, first clear the PDN bit, and then clear the PCADC bit. 2.
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UM10360 NXP Semiconductors Chapter 29: LPC17xx Analog-to-Digital Converter (ADC) 29.4 Pin description Table 529 gives a brief summary of each of ADC related pins. Table 529. ADC pin description Pin Type Description AD0.7 to AD0.0 Input Analog Inputs. The ADC cell can measure the voltage on any of these input signals. Digital signals are disconnected from the ADC input pins when the ADC function is selected on that pin in the Pin Select register.
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UM10360 NXP Semiconductors Chapter 29: LPC17xx Analog-to-Digital Converter (ADC) 29.5 Register description The A/D Converter registers are shown in Table 530. Table 530. ADC registers Generic Name Description Access Reset AD0 Name & value[1] Address ADCR A/D Control Register. The ADCR register must be written to select the operating mode before A/D conversion can occur. R/W 1 AD0CR 0x4003 4000 ADGDR A/D Global Data Register.
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UM10360 NXP Semiconductors Chapter 29: LPC17xx Analog-to-Digital Converter (ADC) 29.5.1 A/D Control Register (AD0CR - 0x4003 4000) Table 531: A/D Control Register (AD0CR - address 0x4003 4000) bit description Bit Symbol Value Description Reset value 7:0 SEL Selects which of the AD0.7:0 pins is (are) to be sampled and converted. For AD0, bit 0 selects Pin AD0.0, and bit 7 selects pin AD0.7. In software-controlled mode, only one of these bits should be 1.
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UM10360 NXP Semiconductors Chapter 29: LPC17xx Analog-to-Digital Converter (ADC) 29.5.2 A/D Global Data Register (AD0GDR - 0x4003 4004) The A/D Global Data Register holds the result of the most recent A/D conversion that has completed, and also includes copies of the status flags that go with that conversion. Results of ADC conversion can be read in one of two ways. One is to use the A/D Global Data Register to read all data from the ADC. Another is to use the A/D Channel Data Registers.
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UM10360 NXP Semiconductors Chapter 29: LPC17xx Analog-to-Digital Converter (ADC) Table 533: A/D Status register (AD0INTEN - address 0x4003 400C) bit description Bit Symbol Value Description Reset value 3 ADINTEN3 0 Completion of a conversion on ADC channel 3 will not generate an interrupt. 0 1 Completion of a conversion on ADC channel 3 will generate an interrupt. 4 ADINTEN4 0 Completion of a conversion on ADC channel 4 will not generate an interrupt.
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UM10360 NXP Semiconductors Chapter 29: LPC17xx Analog-to-Digital Converter (ADC) 29.5.5 A/D Status register (ADSTAT - 0x4003 4030) The A/D Status register allows checking the status of all A/D channels simultaneously. The DONE and OVERRUN flags appearing in the ADDRn register for each A/D channel are mirrored in ADSTAT. The interrupt flag (the logical OR of all DONE flags) is also found in ADSTAT.
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UM10360 NXP Semiconductors Chapter 29: LPC17xx Analog-to-Digital Converter (ADC) 29.6 Operation Once an ADC conversion is started, it cannot be interrupted. A new software write to launch a new conversion or a new edge-trigger event will be ignored while the previous conversion is in progress. 29.6.1 Hardware-triggered conversion If the BURST bit in the ADCR is 0 and the START field contains 010-111, the ADC will start a conversion when a transition occurs on a selected pin or Timer Match signal.
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UM10360 Chapter 30: LPC17xx Digital-to-Analog Converter (DAC) Rev. 2 — 19 August 2010 User manual 30.1 Basic configuration The DAC is configured using the following registers: 1. Power: The DAC is always connected to VDDA. Register access is determined by PINSEL and PINMODE settings (see below). 2. Clock: In the PCLKSEL0 register (Table 40), select PCLK_DAC. 3. Pins: Enable the DAC pin through the PINSEL registers. Select pin mode for port pin with DAC through the PINMODE registers (Section 8.5).
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UM10360 NXP Semiconductors Chapter 30: LPC17xx Digital-to-Analog Converter (DAC) 30.4 Register description The DAC registers are shown in Table 538. Note that the DAC does not have a control bit in the PCONP register. To enable the DAC, its output must be selected to appear on the related pin, P0.26, by configuring the PINSEL1 register. See Section 8.5.2 “Pin Function Select Register 1 (PINSEL1 - 0x4002 C004)”. the DAC must be enabled in this manner prior to accessing any DAC registers. Table 538.
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UM10360 NXP Semiconductors Chapter 30: LPC17xx Digital-to-Analog Converter (DAC) Table 540. D/A Control register (DACCTRL - address 0x4008 C004) bit description Bit Symbol 0 INT_DMA_REQ 0 This bit is cleared on any write to the DACR register. 1 This bit is set by hardware when the timer times out. 0 DACR double-buffering is disabled. 1 When this bit and the CNT_ENA bit are both set, the double-buffering feature in the DACR register will be enabled.
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UM10360 NXP Semiconductors Chapter 30: LPC17xx Digital-to-Analog Converter (DAC) If either the CNT_ENA or the DBLBUF_ENA bits are 0, any writes to the DACR address will go directly to the DACR register. pbus CNTVAL pbus pbus_wr_toDACR pbus 16 pbus 3 DMA_ena 2 cnt_ena 1 set_intrpt pbus_wr_to_DACR S C 0 LD PRE-BUFFER EN LD COUNTER dblbuf_ena 16 zero intrptDMA_req set_intrpt ena_cnt_and_dblbuf 1 0 MUX pbus_wr_to_DACR LD DACR pbus DAC value Fig 133.
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UM10360 Chapter 31: LPC17xx General Purpose DMA (GPDMA) Rev. 2 — 19 August 2010 User manual 31.1 Basic configuration The GPDMA is configured using the following registers: 1. Power: In the PCONP register (Table 46), set bit PCGPDMA. Remark: On reset, the GPDMA is disabled (PCGPDMA = 0). 2. Clock: see Table 38. 3. Interrupts: Interrupts are enabled in the NVIC using the appropriate Interrupt Set Enable register. 4. Programming: see Section 31.6. 31.
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UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) • Big-endian and little-endian support. The DMA Controller defaults to little-endian mode on reset. • An interrupt to the processor can be generated on a DMA completion or when a DMA error has occurred. • Raw interrupt status. The DMA error and DMA count raw interrupt status can be read prior to masking. • DMA can operate in Sleep mode. (Note that in Sleep mode the GPDMA cannot access the flash memory). 31.
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UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) 31.4.1.2 Control logic and register bank The register block stores data written or to be read across the AHB interface. 31.4.1.3 DMA request and response interface See Section 31.4.2 for information on the DMA request and response interface. 31.4.1.4 Channel logic and channel register bank The channel logic and channel register bank contains registers and logic required for each DMA channel. 31.4.1.
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UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) Table 542.
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UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) Table 542.
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UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) 31.4.1.7 Channel hardware Each stream is supported by a dedicated hardware channel, including source and destination controllers, as well as a FIFO. This enables better latency than a DMA controller with only a single hardware channel shared between several DMA streams and simplifies the control logic. 31.4.1.8 DMA request priority DMA channel priority is fixed.
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UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) DMACTC[15:0] — DMA terminal count signals. The DMACTC signal can be used by the DMA controller to indicate to the peripheral that the DMA transfer is complete. 31.4.2.3 DMA request connections The connection of the GPDMA to the supported peripheral devices depends on the DMA functions implemented in those peripherals. Table 543 shows the DMA Request numbers used by the supported peripherals.
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UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) 31.5 Register description The DMA Controller supports 8 channels. Each channel has registers specific to the operation of that channel. Other registers controls aspects of how source peripherals relate to the DMA Controller. There are also global DMA control and status registers. The DMA Controller registers are shown in Table 544. Table 544.
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UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) Table 544.
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UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) 31.5.1 DMA Interrupt Status register (DMACIntStat - 0x5000 4000) The DMACIntStat Register is read-only and shows the status of the interrupts after masking. A 1 bit indicates that a specific DMA channel interrupt request is active. The request can be generated from either the error or terminal count interrupt requests. Table 545 shows the bit assignments of the DMACIntStat Register. Table 545.
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UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) Table 548. DMA Interrupt Error Status register (DMACIntErrStat - 0x5000 400C) Bit Name Function 7:0 IntErrStat Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. 31:8 - Reserved, user software should not write ones to reserved bits.
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UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) Table 551. DMA Raw Error Interrupt Status register (DMACRawIntErrStat - 0x5000 4018) Bit Name Function 7:0 RawIntErrStat Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
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UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) 31.5.10 DMA Software Single Request register (DMACSoftSReq - 0x5000 4024) The DMACSoftSReq Register is read/write and enables DMA single transfer requests to be generated by software. A DMA request can be generated for each source by writing a 1 to the corresponding register bit. A register bit is cleared when the transaction has completed. Reading the register indicates which sources are requesting single DMA transfers.
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UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) Table 556. DMA Software Last Single Request register (DMACSoftLSReq - 0x5000 402C) Bit Name Function 15:0 SoftLSReq Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.
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UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) 31.5.15 DMA Request Select register (DMAReqSel - 0x400F C1C4) DMAReqSel is a read/write register that allows selecting between UART or Timer DMA requests for DMA inputs 8 through 15. Table 559 shows the bit assignments of the DMAReqSel Register. Table 559. DMA Request Select register (DMAReqSel - 0x400F C1C4) Bit Name Function 0 DMASEL08 Selects the DMA request for GPDMA input 8: 0 - UART0 TX is selected.
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UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) 31.5.17 DMA Channel Source Address registers (DMACCxSrcAddr 0x5000 41x0) The eight read/write DMACCxSrcAddr Registers (DMACC0SrcAddr to DMACC7SrcAddr) contain the current source address (byte-aligned) of the data to be transferred. Each register is programmed directly by software before the appropriate channel is enabled. When the DMA channel is enabled this register is updated: • As the source address is incremented.
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UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) Table 562. DMA Channel Linked List Item registers (DMACCxLLI - 0x5000 41x8) Bit Name Function 1:0 - Reserved, and must be written as 0. 31:2 LLI Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0. 31.5.
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UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) Table 563. DMA channel control registers (DMACCxControl - 0x5000 41xC) Bit Name Function 11:0 TransferSize Transfer size. This field sets the size of the transfer. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus.
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UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) Table 563. DMA channel control registers (DMACCxControl - 0x5000 41xC) …continued Bit Name Function 26 SI Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer. 27 DI Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer.
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UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) Table 564. DMA Channel Configuration registers (DMACCxConfig - 0x5000 41x0) Bit Name Function 0 E Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit.
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UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) 31.5.21.1 Lock control The lock control may set the lock bit by writing a 1 to bit 16 of the DMACCxConfig Register. When a burst occurs, the AHB arbiter will not de-grant the master during the burst until the lock is de-asserted. The DMA Controller can be locked for a a single burst such as a long source fetch burst or a long destination drain burst.
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UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) 31.6 Using the DMA controller 31.6.1 Programming the DMA controller All accesses to the DMA Controller internal register must be word (32-bit) reads and writes. 31.6.1.1 Enabling the DMA controller To enable the DMA controller set the Enable bit in the DMACConfig register. 31.6.1.
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UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) 1. Read the DMACEnbldChns controller register and find out which channels are inactive. 2. Choose an inactive channel that has the required priority. 3. Program the DMA controller 31.6.1.6 Halting a DMA channel Set the halt bit in the relevant DMA channel configuration register. The current source request is serviced. Any further source DMA request is ignored until the halt bit is cleared. 31.6.1.7 Programming a DMA channel 1.
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UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) Table 566. DMA request signal usage Transfer direction Request generator Flow controller Memory-to-peripheral Peripheral DMA Controller Peripheral-to-memory Peripheral DMA Controller Memory-to-memory DMA Controller DMA Controller Source peripheral to destination peripheral Source peripheral and destination peripheral DMA Controller 31.6.2.
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UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) 7. When the destination DMA request goes active and there is data in the DMA Controller FIFO, transfer data into the destination peripheral. 8. If an error occurs while transferring the data, an error interrupt is generated, the DMA stream is disabled, and the flow sequence ends. 9. If the transfer has completed it is indicated by the transfer count reaching 0.
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UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) 31.6.3.1 Hardware interrupt sequence flow When a DMA interrupt request occurs, the Interrupt Service Routine needs to: 1. Read the DMACIntTCStat Register to determine whether the interrupt was generated due to the end of the transfer (terminal count). A 1 bit indicates that the transfer completed. If more than one request is active, it is recommended that the highest priority channels be checked first. 2.
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UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) 31.6.5.1 Linked list items A Linked List Item (LLI) consists of four words. These words are organized in the following order: 1. DMACCxSrcAddr. 2. DMACCxDestAddr. 3. DMACCxLLI. 4. DMACCxControl. Note: The DMACCxConfig DMA channel Configuration Register is not part of the linked list item. 31.6.5.1.1 Programming the DMA controller for scatter/gather DMA To program the DMA Controller for scatter/gather DMA: 1.
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UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) Linked List Array LLI1 Source address 0x2002 0000 Destination address Next LLI address Control information LLI2 Source address 0x2002 0010 Destination address Next LLI address Control information LLI3 Source address 0x2002 0020 Destination address Next LLI address Control information = 0x 2002 A200 = peripheral = 0x2002 0010 = length 3072 = 0x 2002 B200 = peripheral = 0x2002 0020 = length 3072 = 0x 2002 C200 = peripheral = 0x2002
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UM10360 NXP Semiconductors Chapter 31: LPC17xx General Purpose DMA (GPDMA) • • • • • • Source start address 0x2003 1200. Destination address set to the destination peripheral address. Transfer width, word (32-bit). Transfer size, 3072 bytes (0xC00). Source and destination burst sizes, 16 transfers. Next LLI address, 0x0. Because the next LLI address is set to zero, this is the last descriptor, and the DMA channel is disabled after transferring the last item of data.
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UM10360 Chapter 32: LPC17xx Flash memory interface and programming Rev. 2 — 19 August 2010 User manual 32.1 Introduction The boot loader controls initial operation after reset and also provides the tools for programming the flash memory. This could be initial programming of a blank device, erasure and re-programming of a previously programmed device, or programming of the flash memory by the application program in a running system. 32.
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UM10360 NXP Semiconductors Chapter 32: LPC17xx Flash memory interface and programming A hardware flash signature generation capability is built into the flash memory. this feature can be used to create a signature that can then be used to verify flash contents. Details of flash signature generation are in Section 32.10. 32.3.1 Memory map after any reset When a user program begins execution after reset, the interrupt vectors are set to point to the beginning of flash memory. Fig 136.
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UM10360 NXP Semiconductors Chapter 32: LPC17xx Flash memory interface and programming sends an ASCII string ("Synchronized") to the host. In response to this the host should send the same string ("Synchronized"). The auto-baud routine looks at the received characters to verify synchronization. If synchronization is verified then "OK" string is sent to the host. The host should respond by sending the crystal frequency (in kHz) at which the part is running.
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UM10360 NXP Semiconductors Chapter 32: LPC17xx Flash memory interface and programming 32.3.2.4 ISP flow control A software XON/XOFF flow control scheme is used to prevent data loss due to buffer overrun. When the data arrives rapidly, the ASCII control character DC3 (0x13) is sent to stop the flow of data. Data flow is resumed by sending the ASCII control character DC1 (0x11). The host should also support the same flow control scheme. 32.3.2.
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UM10360 NXP Semiconductors Chapter 32: LPC17xx Flash memory interface and programming 32.4 Boot process flowchart RESET INITIALIZE CRP1/2/3 ENABLED? no ENABLE DEBUG yes WATCHDOG FLAG SET? yes A no yes USER CODE VALID? no CRP3 ENABLED? yes EXECUTE INTERNAL USER CODE Enter ISP MODE? (P2.
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UM10360 NXP Semiconductors Chapter 32: LPC17xx Flash memory interface and programming 32.5 Sector numbers Some IAP and ISP commands operate on "sectors" and specify sector numbers. The following table indicate the correspondence between sector numbers and memory addresses for LPC17xx devices containing 32, 64, 128, 256 and 512 kB of flash respectively. IAP and ISP routines are located in the Boot ROM. Table 567.
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UM10360 NXP Semiconductors Chapter 32: LPC17xx Flash memory interface and programming 32.6 Code Read Protection (CRP) Code Read Protection is a mechanism that allows user to enable different levels of security in the system so that access to the on-chip flash and use of the ISP can be restricted. When needed, CRP is invoked by programming a specific pattern in flash location at 0x000002FC. IAP commands are not affected by the code read protection.
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UM10360 NXP Semiconductors Chapter 32: LPC17xx Flash memory interface and programming Table 569. Code Read Protection hardware/software interaction CRP option User Code Valid P2.
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UM10360 NXP Semiconductors Chapter 32: LPC17xx Flash memory interface and programming 32.7 ISP commands The following commands are accepted by the ISP command handler. Detailed status codes are supported for each command. The command handler sends the return code INVALID_COMMAND when an undefined command is received. Commands and return codes are in ASCII format.
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UM10360 NXP Semiconductors Chapter 32: LPC17xx Flash memory interface and programming 32.7.2 Set Baud Rate Table 572. ISP Set Baud Rate command Command Input B Baud Rate: 9600 | 19200 | 38400 | 57600 | 115200 | 230400 Stop bit: 1 | 2 Return Code CMD_SUCCESS | INVALID_BAUD_RATE | INVALID_STOP_BIT | PARAM_ERROR Description This command is used to change the baud rate. The new baud rate is effective after the command handler sends the CMD_SUCCESS return code.
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UM10360 NXP Semiconductors Chapter 32: LPC17xx Flash memory interface and programming The ISP command handler compares it with the check-sum of the received bytes. If the check-sum matches, the ISP command handler responds with "OK" to continue further transmission. If the check-sum does not match, the ISP command handler responds with "RESEND". In response the host should retransmit the bytes. Table 575.
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UM10360 NXP Semiconductors Chapter 32: LPC17xx Flash memory interface and programming 32.7.6 Prepare sector(s) for write operation This command makes flash write/erase operation a two step process. Table 577. ISP Prepare sector(s) for write operation command Command P Input Start Sector Number End Sector Number: Should be greater than or equal to start sector number.
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UM10360 NXP Semiconductors Chapter 32: LPC17xx Flash memory interface and programming 32.7.8 Go
Table 579. ISP Go command Command G Input Address: Flash or RAM address from which the code execution is to be started. This address should be on a word boundary. Mode (retained for backward compatibility): T (Execute program in Thumb Mode) | A (not allowed).
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UM10360 NXP Semiconductors Chapter 32: LPC17xx Flash memory interface and programming 32.7.10 Blank check sector(s) Table 581. ISP Blank check sector command Command I Input Start Sector Number: End Sector Number: Should be greater than or equal to start sector number.
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UM10360 NXP Semiconductors Chapter 32: LPC17xx Flash memory interface and programming 32.7.12 Read Boot Code version number Table 584. ISP Read Boot Code version number command Command K Input None Return Code CMD_SUCCESS followed by 2 bytes of boot code version number in ASCII format. It is to be interpreted as .. Description This command is used to read the boot code version number. 32.7.13 Read device serial number Table 585.
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UM10360 NXP Semiconductors Chapter 32: LPC17xx Flash memory interface and programming 32.7.15 ISP Return Codes Table 587. ISP Return Codes Summary UM10360 User manual Return Mnemonic Code Description 0 CMD_SUCCESS Command is executed successfully. Sent by ISP handler only when command given by the host has been completely and successfully executed. 1 INVALID_COMMAND Invalid command. 2 SRC_ADDR_ERROR Source address is not on word boundary.
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UM10360 NXP Semiconductors Chapter 32: LPC17xx Flash memory interface and programming 32.8 IAP commands For in application programming the IAP routine should be called with a word pointer in register r0 pointing to memory (RAM) containing command code and parameters. Result of the IAP command is returned in the result table pointed to by register r1. The user can reuse the command table for result by passing the same pointer in registers r0 and r1.
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UM10360 NXP Semiconductors Chapter 32: LPC17xx Flash memory interface and programming returned in the r0, r1, r2 and r3 registers respectively. Additional parameters are returned indirectly via memory. Some of the IAP calls require more than 4 parameters. If the ARM suggested scheme is used for the parameter passing/returning then it might create problems due to difference in the C compiler implementation from different vendors. The suggested parameter passing scheme reduces such risk.
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UM10360 NXP Semiconductors Chapter 32: LPC17xx Flash memory interface and programming Table 589. IAP Prepare sector(s) for write operation command Command Prepare sector(s) for write operation Input Command code: 5010 Param0: Start Sector Number Param1: End Sector Number (should be greater than or equal to start sector number). Return Code CMD_SUCCESS | BUSY | INVALID_SECTOR Result None Description This command must be executed before executing "Copy RAM to Flash" or "Erase Sector(s)" command.
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UM10360 NXP Semiconductors Chapter 32: LPC17xx Flash memory interface and programming 32.8.3 Erase Sector(s) Table 591. IAP Erase Sector(s) command Command Erase Sector(s) Input Command code: 5210 Param0: Start Sector Number Param1: End Sector Number (should be greater than or equal to start sector number). Param2: CPU Clock Frequency (CCLK) in kHz.
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UM10360 NXP Semiconductors Chapter 32: LPC17xx Flash memory interface and programming 32.8.6 Read Boot Code version number Table 594. IAP Read Boot Code version number command Command Read boot code version number Input Command code: 5510 Parameters: None Return Code CMD_SUCCESS | Result Result0: 2 bytes of boot code version number in ASCII format. It is to be interpreted as . Description This command is used to read the boot code version number. 32.8.
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UM10360 NXP Semiconductors Chapter 32: LPC17xx Flash memory interface and programming 32.8.9 Re-invoke ISP Table 597. Re-invoke ISP Command Compare Input Command code: 5710 Return Code None Result None. Description This command is used to invoke the boot loader in ISP mode. It maps boot vectors, sets PCLK = CCLK / 4, configures UART0 pins Rx and Tx, resets TIMER1 and resets the U0FDR (see Section 14.4.12).
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UM10360 NXP Semiconductors Chapter 32: LPC17xx Flash memory interface and programming 32.10 Flash signature generation The flash module contains a built-in signature generator. This generator can produce a 128-bit signature from a range of flash memory. A typical usage is to verify the flashed contents against a calculated signature (e.g. during programming). The address range for generating a signature must be aligned on flash-word boundaries, i.e. 128-bit boundaries.
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UM10360 NXP Semiconductors Chapter 32: LPC17xx Flash memory interface and programming 32.10.1.1 Signature generation address and control registers These registers control automatic signature generation. A signature can be generated for any part of the flash memory contents. The address range to be used for generation is defined by writing the start address to the signature start address register (FMSSTART) and the stop address to the signature stop address register (FMSSTOP.
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UM10360 NXP Semiconductors Chapter 32: LPC17xx Flash memory interface and programming Table 604. FMSW2 register bit description (FMSW2, address: 0x4008 4034) Bit Symbol Description Reset Value 31:0 SW2[95:64] Word 2 of 128-bit signature (bits 95 to 64). - Table 605. FMSW3 register bit description (FMSW3, address: 0x4008 4038) Bit Symbol Description Reset Value 31:0 SW3[127:96] Word 3 of 128-bit signature (bits 127 to 96). - 32.10.1.
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UM10360 NXP Semiconductors Chapter 32: LPC17xx Flash memory interface and programming 32.10.2 Algorithm and procedure for signature generation Signature generation A signature can be generated for any part of the flash contents. The address range to be used for signature generation is defined by writing the start address to the FMSSTART register, and the stop address to the FMSSTOP register. The signature generation is started by writing a ‘1’ to FMSSTOP.MISR_START.
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UM10360 Chapter 33: LPC17xx JTAG, Serial Wire Debug (SWD), and Trace Rev. 2 — 19 August 2010 User manual 33.1 Features • • • • Supports both standard JTAG and ARM Serial Wire Debug modes. Direct debug access to all memories, registers, and peripherals. No target resources are required for the debugging session. Trace port provides CPU instruction trace capability. Output can be via a 4-bit trace data port, or Serial Wire Viewer. • Eight Breakpoints.
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UM10360 NXP Semiconductors Chapter 33: LPC17xx JTAG, Serial Wire Debug (SWD), and Trace Table 608. JTAG pin description Pin Name Type Description TCK Input JTAG Test Clock. This pin is the clock for debug logic when in the JTAG debug mode. TMS Input JTAG Test Mode Select. The TMS pin selects the next state in the TAP state machine. TDI Input JTAG Test Data In. This is the serial data input for the shift register. TDO Output JTAG Test Data Output.
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UM10360 NXP Semiconductors Chapter 33: LPC17xx JTAG, Serial Wire Debug (SWD), and Trace Another issue is that debug mode changes the way in which reduced power modes are handled by the Cortex-M3 CPU. This causes power modes at the device level to be different from normal modes operation. These differences mean that power measurements should not be made while debugging, the results will be higher than during normal operation in an application.
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UM10360 Chapter 34: Appendix: Cortex-M3 user guide Rev. 2 — 19 August 2010 User manual 34.1 ARM Cortex-M3 User Guide: Introduction The material in this appendix is provided by ARM Limited for inclusion in the User Manuals of devices containing the Cortex-M3 CPU. Minimal changes have been made to reflect implementation options and other distinctions that apply specifically to LPC17xx devices. 34.1.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide To facilitate the design of cost-sensitive devices, the Cortex-M3 processor implements tightly-coupled system components that reduce processor area while significantly improving interrupt handling and system debug capabilities. The Cortex-M3 processor implements a version of the Thumb instruction set, ensuring high code density and reduced program memory requirements.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide LPC17xx devices support JTAG and Serial Wire Debug, Serial Wire Viewer, and include the Embedded Trace Macrocell. See Section 33.1 for additional information. 34.1.1.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2 ARM Cortex-M3 User Guide: Instruction Set 34.2.1 Instruction set summary The processor implements a version of the Thumb instruction set. Table 612 lists the supported instructions.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 612. Cortex-M3 instructions …continued Mnemonic Operands Brief description Flags Page ISB - Instruction Synchronization Barrier - Section 34.2.10.5 IT - If-Then condition block - Section 34.2.9.3 LDM Rn{!}, reglist Load Multiple registers, increment after - Section 34.2.4.6 LDMDB, LDMEA Rn{!}, reglist Load Multiple registers, decrement before - Section 34.2.4.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 612. Cortex-M3 instructions …continued Mnemonic Operands Brief description Flags Page SDIV {Rd,} Rn, Rm Signed Divide - Section 34.2.6.3 SEV - Send Event - Section 34.2.10.9 SMLAL RdLo, RdHi, Rn, Rm Signed Multiply with Accumulate (32 x 32 + 64), 64-bit result - Section 34.2.6.2 SMULL RdLo, RdHi, Rn, Rm Signed Multiply (32 x 32), 64-bit result - Section 34.2.6.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.2 Intrinsic functions ANSI cannot directly access some Cortex-M3 instructions. This section describes intrinsic functions that can generate these instructions, provided by the CMIS and that might be provided by a C compiler. If a C compiler does not support an appropriate intrinsic function, you might have to use inline assembler to access some instructions.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide • • • • • • • • Section 34.2.3.1 “Operands” Section 34.2.3.2 “Restrictions when using PC or SP” Section 34.2.3.3 “Flexible second operand” Section 34.2.3.4 “Shift Operations” Section 34.2.3.5 “Address alignment” Section 34.2.3.6 “PC-relative expressions” Section 34.2.3.7 “Conditional execution” Section 34.2.3.8 “Instruction width selection”. 34.2.3.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Remark: In the constants shown above, X and Y are hexadecimal digits. In addition, in a small number of instructions, constant can take a wider range of values. These are described in the individual instruction descriptions.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide The permitted shift lengths depend on the shift type and the instruction, see the individual instruction description or Section 34.2.3.3. If the shift length is 0, no shift occurs. Register shift operations update the carry flag except when the specified shift length is 0. The following sub-sections describe the various shift operations and how they affect the carry flag.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide • If n is 33 or more and the carry flag is updated, it is updated to 0. 0 0 Carry Flag 0 31 5 4 3 2 1 0 ... Fig 142. LSR#3 34.2.3.4.3 LSL Logical shift left by n bits moves the right-hand 32-n bits of the register Rm, to the left by n places, into the left-hand 32-n bits of the result. And it sets the right-hand n bits of the result to 0. See Figure 143.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide • If n is 32, then the value of the result is same as the value in Rm, and if the carry flag is updated, it is updated to bit[31] of Rm. • ROR with shift length, n, more than 32 is the same as ROR with shift length n-32. Carry Flag 31 5 4 3 2 1 0 ... Fig 144. ROR#3 34.2.3.4.5 RRX Rotate right with extend moves the bits of the register Rm to the right by one bit. And it copies the carry flag into bit[31] of the result.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Unaligned accesses are usually slower than aligned accesses. In addition, some memory regions might not support unaligned accesses. Therefore, ARM recommends that programmers ensure that accesses are aligned. To avoid accidental generation of unaligned accesses, use the UNALIGN_TRP bit in the Configuration and Control Register to trap all unaligned accesses, see Section 34.4.3.8 “Configuration and Control Register”. 34.2.3.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Use the CBZ and CBNZ instructions to compare the value of a register against zero and branch on the result. This section describes: • Section 34.2.3.7.1 “The condition flags” • Section 34.2.3.7.2 “Condition code suffixes”. 34.2.3.7.1 The condition flags The APSR contains the following condition flags: N — Set to 1 when the result of the operation was negative, cleared to 0 otherwise.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 615. Condition code suffixes Suffix Flags Meaning PL N=0 Positive or zero VS V=1 Overflow VC V=0 No overflow HI C = 1 and Z = 0 Higher, unsigned > LS C = 0 or Z = 1 Lower or same, unsigned ≤ GE N=V Greater than or equal, signed ≥ LT N != V Less than, signed < GT Z = 0 and N = V Greater than, signed > LE Z = 1 and N != V Less than or equal, signed ≤ AL Can have any value Always.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.3.8.1 Example: Instruction width selection BCS.W label ; creates a 32-bit instruction even for a short branch ADDS.W R0, R0, R1 ; creates a 32-bit instruction even though the same ; operation can be done by a 16-bit instruction UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 August 2010 © NXP B.V. 2010. All rights reserved.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.4 Memory access instructions Table 616 shows the memory access instructions: Table 616. Memory access instructions UM10360 User manual Mnemonic Brief description See ADR Load PC-relative address Section 34.2.4.1 CLREX Clear Exclusive Section 34.2.4.9 LDM{mode} Load Multiple registers Section 34.2.4.6 LDR{type} Load Register using immediate offset Section 34.2.4.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.4.1 ADR Load PC-relative address. 34.2.4.1.1 Syntax ADR{cond} Rd, label where: cond is an optional condition code, see Section 34.2.3.7 “Conditional execution”. Rd is the destination register. label is a PC-relative expression. See Section 34.2.3.6 “PC-relative expressions”. 34.2.4.1.2 Operation ADR determines the address by adding an immediate value to the PC, and writes the result to the destination register.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.4.2 LDR and STR, immediate offset Load and Store with immediate offset, pre-indexed immediate offset, or post-indexed immediate offset. 34.2.4.2.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide [Rn, #offset] • Pre-indexed addressing The offset value is added to or subtracted from the address obtained from the register Rn. The result is used as the address for the memory access and written back into the register Rn. The assembly language syntax for this mode is: [Rn, #offset]! • Post-indexed addressing The address obtained from the register Rn is used as the address for the memory access.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.4.2.5 Examples LDR LDRNE STR STRH LDRD STRD UM10360 User manual R8, [R10] R2, [R5, #960]! ; ; ; ; R2, [R9,#const-struc] ; ; R3, [R4], #4 ; ; R8, R9, [R3, #0x20] ; ; ; R0, R1, [R8], #-16 ; ; ; Loads R8 from the address in R10. Loads (conditionally) R2 from a word 960 bytes above the address in R5, and increments R5 by 960. const-struc is an expression evaluating to a constant in the range 0-4095.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.4.3 LDR and STR, register offset Load and Store with register offset. 34.2.4.3.1 Syntax op{type}{cond} Rt, [Rn, Rm {, LSL #n}] where: op is one of: LDR: Load Register. STR: Store Register. type is one of: B: unsigned byte, zero extend to 32 bits on loads. SB: signed byte, sign extend to 32 bits (LDR only). H: unsigned halfword, zero extend to 32 bits on loads. SH: signed halfword, sign extend to 32 bits (LDR only).
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide • bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this halfword-aligned address • if the instruction is conditional, it must be the last instruction in the IT block. 34.2.4.3.4 Condition flags These instructions do not change the flags. 34.2.4.3.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.4.4 LDR and STR, unprivileged Load and Store with unprivileged access. 34.2.4.4.1 Syntax op{type}T{cond} Rt, [Rn {, #offset}] ; immediate offset where: op is one of: LDR: Load Register. STR: Store Register. type is one of: B: unsigned byte, zero extend to 32 bits on loads. SB: signed byte, sign extend to 32 bits (LDR only). H: unsigned halfword, zero extend to 32 bits on loads.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.4.4.5 Examples STRBTEQ R4, [R7] LDRHT UM10360 User manual R2, [R2, #8] ; ; ; ; Conditionally store least significant byte in R4 to an address in R7, with unprivileged access Load halfword value from an address equal to sum of R2 and 8 into R2, with unprivileged access All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 August 2010 © NXP B.V. 2010. All rights reserved.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.4.5 LDR, PC-relative Load register from memory. 34.2.4.5.1 Syntax LDR{type}{cond} Rt, label LDRD{cond} Rt, Rt2, label ; Load two words type is one of: B: unsigned byte, zero extend to 32 bits on loads. SB: signed byte, sign extend to 32 bits (LDR only). H: unsigned halfword, zero extend to 32 bits on loads. SH: signed halfword, sign extend to 32 bits (LDR only). —: omit, for word.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide • bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this halfword-aligned address • if the instruction is conditional, it must be the last instruction in the IT block. 34.2.4.5.4 Condition flags These instructions do not change the flags. 34.2.4.5.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.4.6 LDM and STM Load and Store Multiple registers. 34.2.4.6.1 Syntax op{addr_mode}{cond} Rn{!}, reglist where: op is one of: LDM: Load Multiple registers. STM: Store Multiple registers. addr_mode is any one of the following: IA: Increment address After each access. This is the default. DB: Decrement address Before each access. cond is an optional condition code, see Section 34.2.3.7 “Conditional execution”.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide For LDMDB, LDMEA, STMDB, and STMFD the memory addresses used for the accesses are at 4-byte intervals ranging from Rn to Rn - 4 * (n-1), where n is the number of registers in reglist. The accesses happen in order of decreasing register numbers, with the highest numbered register using the highest memory address and the lowest number register using the lowest memory address.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.4.7 PUSH and POP Push registers onto, and pop registers off a full-descending stack. 34.2.4.7.1 Syntax PUSH{cond} reglist POP{cond} reglist where: cond is an optional condition code, see Section 34.2.3.7 “Conditional execution”. reglist is a non-empty list of registers, enclosed in braces. It can contain register ranges. It must be comma separated if it contains more than one register or register range.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.4.8 LDREX and STREX Load and Store Register Exclusive. 34.2.4.8.1 Syntax LDREX{cond} Rt, [Rn {, #offset}] STREX{cond} Rd, Rt, [Rn {, #offset}] LDREXB{cond} Rt, [Rn] STREXB{cond} Rd, Rt, [Rn] LDREXH{cond} Rt, [Rn] STREXH{cond} Rd, Rt, [Rn] where: cond is an optional condition code, see Section 34.2.3.7 “Conditional execution”. Rd is the destination register for the returned status. Rt is the register to load or store.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide • • • • 34.2.4.8.4 do not use PC do not use SP for Rd and Rt for STREX, Rd must be different from both Rt and Rn the value of offset must be a multiple of four in the range 0-1020. Condition flags These instructions do not change the flags. 34.2.4.8.5 Examples MOV R1, #0x1 LDREX CMP ITT STREXEQ CMPEQ BNE ....
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.4.9 CLREX Clear Exclusive. 34.2.4.9.1 Syntax CLREX{cond} where: cond is an optional condition code, see Section 34.2.3.7 “Conditional execution”. 34.2.4.9.2 Operation Use CLREX to make the next STREX, STREXB, or STREXH instruction write 1 to its destination register and fail to perform the store.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.5 General data processing instructions Table 619 shows the data processing instructions: Table 619. Data processing instructions UM10360 User manual Mnemonic Brief description See ADC Add with Carry Section 34.2.5.1 ADD Add Section 34.2.5.1 ADDW Add Section 34.2.5.1 AND Logical AND Section 34.2.5.2 ASR Arithmetic Shift Right Section 34.2.5.3 BIC Bit Clear Section 34.2.5.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.5.1 ADD, ADC, SUB, SBC, and RSB Add, Add with carry, Subtract, Subtract with carry, and Reverse Subtract. 34.2.5.1.1 Syntax op{S}{cond} {Rd,} Rn, Operand2 op{cond} {Rd,} Rn, #imm12 ; ADD and SUB only where: op is one of: ADD: Add. ADC: Add with Carry. SUB: Subtract. RSB: Reverse Subtract. S: is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation, see Section 34.2.3.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide – Rn must also be SP – any shift in Operand2 must be limited to a maximum of 3 bits using LSL • Rn can be SP only in ADD and SUB • Rd can be PC only in the cond instruction where: – you must not specify the S suffix – Rm must not be PC and must not be SP – if the instruction is conditional, it must be the last instruction in the IT block • with the exception of the cond instruction, Rn can be PC only in ADD and SUB, and only with the
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 96-bit subtraction: SUBS R6, R6, R9 SBCS R9, R2, R1 SBC R2, R8, R11 UM10360 User manual ; subtract the least significant words ; subtract the middle words with carry ; subtract the most significant words with carry All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 August 2010 © NXP B.V. 2010. All rights reserved.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.5.2 AND, ORR, EOR, BIC, and ORN Logical AND, OR, Exclusive OR, Bit Clear, and OR NOT. 34.2.5.2.1 Syntax op{S}{cond} {Rd,} Rn, Operand2 where: op is one of: AND: logical AND. ORR: logical OR, or bit set. EOR: logical Exclusive OR. BIC: logical AND NOT, or bit clear. ORN: logical OR NOT. S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation, see Section 34.2.3.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide EORS BIC ORN ORNS UM10360 User manual R7, R0, R7, R7, R11, #0x18181818 R1, #0xab R11, R14, ROR #4 R11, R14, ASR #32 All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 August 2010 © NXP B.V. 2010. All rights reserved.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.5.3 ASR, LSL, LSR, ROR, and RRX Arithmetic Shift Right, Logical Shift Left, Logical Shift Right, Rotate Right, and Rotate Right with Extend. 34.2.5.3.1 Syntax op{S}{cond} Rd, Rm, Rs op{S}{cond} Rd, Rm, #n RRX{S}{cond} Rd, Rm where: op is one of: ASR: Arithmetic Shift Right. LSL: Logical Shift Left. LSR: Logical Shift Right. ROR: Rotate Right. S is an optional suffix.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.5.3.4 Condition flags If S is specified: • these instructions update the N and Z flags according to the result • the C flag is updated to the last bit shifted out, except when the shift length is 0, see Section 34.2.3.4 “Shift Operations”. 34.2.5.3.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.5.4 CLZ Count Leading Zeros. 34.2.5.4.1 Syntax CLZ{cond} Rd, Rm where: cond is an optional condition code, see Section 34.2.3.7. Rd is the destination register. Rm is the operand register. 34.2.5.4.2 Operation The CLZ instruction counts the number of leading zeros in the value in Rm and returns the result in Rd. The result value is 32 if no bits are set in the source register, and zero if bit[31] is set. 34.2.5.4.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.5.5 CMP and CMN Compare and Compare Negative. 34.2.5.5.1 Syntax CMP{cond} Rn, Operand2 CMN{cond} Rn, Operand2 where: cond is an optional condition code, see Section 34.2.3.7. Rn is the register holding the first operand. Operand2 is a flexible second operand. See Flexible second operand on page 3-10for details of the options. 34.2.5.5.2 Operation These instructions compare the value in a register with Operand2.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.5.6 MOV and MVN Move and Move NOT. 34.2.5.6.1 Syntax MOV{S}{cond} Rd, Operand2 MOV{cond} Rd, #imm16 MVN{S}{cond} Rd, Operand2 where: S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation, see Section 34.2.3.7. cond is an optional condition code, see Section 34.2.3.7. Rd is the destination register. Operand2 is a flexible second operand.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.5.6.3 Restrictions You can use SP and PC only in the MOV instruction, with the following restrictions: • the second operand must be a register without shift • you must not specify the S suffix. When Rd is PC in a MOV instruction: • bit[0] of the value written to the PC is ignored • a branch occurs to the address created by forcing bit[0] of that value to 0.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.5.7 MOVT Move Top. 34.2.5.7.1 Syntax MOVT{cond} Rd, #imm16 where: cond is an optional condition code, see Section 34.2.3.7. Rd is the destination register. imm16 is a 16-bit immediate constant. 34.2.5.7.2 Operation MOVT writes a 16-bit immediate value, imm16, to the top halfword, Rd[31:16], of its destination register. The write does not affect Rd[15:0].
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.5.8 REV, REV16, REVSH, and RBIT Reverse bytes and Reverse bits. 34.2.5.8.1 Syntax op{cond} Rd, Rn where: op is any of: REV Reverse byte order in a word. REV16 Reverse byte order in each halfword independently. REVSH Reverse byte order in the bottom halfword, and sign extend to RBIT Reverse the bit order in a 32-bit word. cond is an optional condition code, see Section 34.2.3.7. Rd is the destination register.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.5.9 TST and TEQ Test bits and Test Equivalence. 34.2.5.9.1 Syntax TST{cond} Rn, Operand2 TEQ{cond} Rn, Operand2 where: cond is an optional condition code, see Section 34.2.3.7 “Conditional execution”. Rn is the register holding the first operand. Operand2 is a flexible second operand. See Section 34.2.3.3 for details of the options. 34.2.5.9.2 Operation These instructions test the value in a register against Operand2.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.6 Multiply and divide instructions Table 620 shows the multiply and divide instructions: Table 620. Multiply and divide instructions UM10360 User manual Mnemonic Brief description See MLA Multiply with Accumulate, 32-bit result Section 34.2.6.1 MLS Multiply and Subtract, 32-bit result Section 34.2.6.1 MUL Multiply, 32-bit result Section 34.2.6.1 SDIV Signed Divide Section 34.2.6.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.6.1 MUL, MLA, and MLS Multiply, Multiply with Accumulate, and Multiply with Subtract, using 32-bit operands, and producing a 32-bit result. 34.2.6.1.1 Syntax MUL{S}{cond} {Rd,} Rn, Rm ; Multiply MLA{cond} Rd, Rn, Rm, Ra ; Multiply with accumulate MLS{cond} Rd, Rn, Rm, Ra ; Multiply with subtract where: cond is an optional condition code, see Section 34.2.3.7 “Conditional execution”. S is an optional suffix.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.6.1.5 Examples MUL MLA MULS MULLT MLS UM10360 User manual R10, R2, R5 R10, R2, R1, R5 R0, R2, R2 R2, R3, R2 R4, R5, R6, R7 ; ; ; ; ; Multiply, R10 Multiply with Multiply with Conditionally Multiply with All information provided in this document is subject to legal disclaimers. Rev.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.6.2 UMULL, UMLAL, SMULL, and SMLAL Signed and Unsigned Long Multiply, with optional Accumulate, using 32-bit operands and producing a 64-bit result. 34.2.6.2.1 Syntax op{cond} RdLo, RdHi, Rn, Rm where: op is one of: UMULL: Unsigned Long Multiply. UMLAL: Unsigned Long Multiply, with Accumulate. SMULL: Signed Long Multiply. SMLAL: Signed Long Multiply, with Accumulate. cond is an optional condition code, see Section 34.2.3.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.6.2.5 Examples UMULL SMLAL UM10360 User manual R0, R4, R5, R6 R4, R5, R3, R8 ; Unsigned (R4,R0) = R5 x R6 ; Signed (R5,R4) = (R5,R4) + R3 x R8 All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 August 2010 © NXP B.V. 2010. All rights reserved.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.6.3 SDIV and UDIV Signed Divide and Unsigned Divide. 34.2.6.3.1 Syntax SDIV{cond} {Rd,} Rn, Rm UDIV{cond} {Rd,} Rn, Rm where: cond is an optional condition code, see Section 34.2.3.7 “Conditional execution”. Rd is the destination register. If Rd is omitted, the destination register is Rn. Rn is the register holding the value to be divided. Rm is a register holding the divisor. 34.2.6.3.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.7 Saturating instructions This section describes the saturating instructions, SSAT and USAT. 34.2.7.1 SSAT and USAT Signed Saturate and Unsigned Saturate to any bit position, with optional shift before saturating. 34.2.7.1.1 Syntax op{cond} Rd, #n, Rm {, shift #s} where: op is one of: SSAT Saturates a signed value to a signed range. USAT Saturates a signed value to an unsigned range.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide • otherwise, the result returned is the same as the value to be saturated. If the returned result is different from the value to be saturated, it is called saturation. If saturation occurs, the instruction sets the Q flag to 1 in the APSR. Otherwise, it leaves the Q flag unchanged. To clear the Q flag to 0, you must use the MSR instruction, see Section 34.2.10.7. To read the state of the Q flag, use the MRS instruction, see Section 34.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.8 Bitfield instructions Table 621 shows the instructions that operate on adjacent sets of bits in registers or bitfields: Table 621. Packing and unpacking instructions UM10360 User manual Mnemonic Brief description See BFC Bit Field Clear Section 34.2.8.1 BFI Bit Field Insert Section 34.2.8.1 SBFX Signed Bit Field Extract Section 34.2.8.2 SXTB Sign extend a byte Section 34.2.8.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.8.1 BFC and BFI Bit Field Clear and Bit Field Insert. 34.2.8.1.1 Syntax BFC{cond} Rd, #lsb, #width BFI{cond} Rd, Rn, #lsb, #width where: cond is an optional condition code, see Section 34.2.3.7 “Conditional execution”. Rd is the destination register. Rn is the source register. lsb is the position of the least significant bit of the bitfield. lsb must be in the range 0 to 31.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.8.2 SBFX and UBFX Signed Bit Field Extract and Unsigned Bit Field Extract. 34.2.8.2.1 Syntax SBFX{cond} Rd, Rn, #lsb, #width UBFX{cond} Rd, Rn, #lsb, #width where: cond is an optional condition code, see Section 34.2.3.7 “Conditional execution”. Rd is the destination register. Rn is the source register. lsb is the position of the least significant bit of the bitfield. lsb must be in the range 0 to 31.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.8.3 SXT and UXT Sign extend and Zero extend. 34.2.8.3.1 Syntax SXTextend{cond} {Rd,} Rm {, ROR #n} UXTextend{cond} {Rd}, Rm {, ROR #n} where: extend is one of: B: Extends an 8-bit value to a 32-bit value. H: Extends a 16-bit value to a 32-bit value. cond is an optional condition code, see Section 34.2.3.7 “Conditional execution”. Rd is the destination register. Rm is the register holding the value to extend.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.8.3.5 Examples SXTH R4, R6, ROR #16 ; ; ; UXTB R3, R10 ; ; UM10360 User manual Rotate R6 right by 16 bits, then obtain the lower halfword of the result and then sign extend to 32 bits and write the result to R4. Extract lowest byte of the value in R10 and zero extend it, and write the result to R3 All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 August 2010 © NXP B.V. 2010.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.9 Branch and control instructions Table 622 shows the branch and control instructions: Table 622. Branch and control instructions UM10360 User manual Mnemonic Brief description See B Branch Section 34.2.9.1 BL Branch with Link Section 34.2.9.1 BLX Branch indirect with Link Section 34.2.9.1 BX Branch indirect Section 34.2.9.1 CBNZ Compare and Branch if Non Zero Section 34.2.9.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.9.1 B, BL, BX, and BLX Branch instructions. 34.2.9.1.1 Syntax B{cond} label BL{cond} label BX{cond} Rm BLX{cond} Rm where: B is branch (immediate). BL is branch with link (immediate). BX is branch indirect (register). BLX is branch indirect with link (register). cond is an optional condition code, see Section 34.2.3.7 “Conditional execution”. label is a PC-relative expression. See Section 34.2.3.6 “PC-relative expressions”.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.9.1.3 Restrictions The restrictions are: • do not use PC in the BLX instruction • for BX and BLX, bit[0] of Rm must be 1 for correct execution but a branch occurs to the target address created by changing bit[0] to 0 • when any of these instructions is inside an IT block, it must be the last instruction of the IT block. Bcond is the only conditional instruction that is not required to be inside an IT block.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.9.2 CBZ and CBNZ Compare and Branch on Zero, Compare and Branch on Non-Zero. 34.2.9.2.1 Syntax CBZ Rn, label CBNZ Rn, label where: Rn is the register holding the operand. label is the branch destination. 34.2.9.2.2 Operation Use the CBZ or CBNZ instructions to avoid changing the condition code flags and to reduce the number of instructions.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.9.3 IT If-Then condition instruction. 34.2.9.3.1 Syntax IT{x{y{z}}} cond where: x specifies the condition switch for the second instruction in the IT block. y specifies the condition switch for the third instruction in the IT block. z specifies the condition switch for the fourth instruction in the IT block. cond specifies the condition for the first instruction in the IT block.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide • CPSID and CPSIE. Other restrictions when using an IT block are: • a branch or any instruction that modifies the PC must either be outside an IT block or must be the last instruction inside the IT block.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide IT ADD UM10360 User manual NE R0, R0, R1 ; Next instruction is conditional ; Syntax error: no condition code used in IT block All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 August 2010 © NXP B.V. 2010. All rights reserved.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.9.4 TBB and TBH Table Branch Byte and Table Branch Halfword. 34.2.9.4.1 Syntax TBB [Rn, Rm] TBH [Rn, Rm, LSL #1] where: Rn is the register containing the address of the table of branch lengths. If Rn is PC, then the address of the table is the address of the byte immediately following the TBB or TBH instruction. Rm is the index register. This contains an index into the table.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide TBH [PC, R1, LSL #1] ; R1 is the index, PC is used as base of the ; branch table BranchTable_H DCI ((CaseA - BranchTable_H)/2) ; CaseA offset calculation DCI ((CaseB - BranchTable_H)/2) ; CaseB offset calculation DCI ((CaseC - BranchTable_H)/2) ; CaseC offset calculation CaseA ; an instruction sequence follows CaseB ; an instruction sequence follows CaseC ; an instruction sequence follows UM10360 User manual All information provi
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.10 Miscellaneous instructions Table 624 shows the remaining Cortex-M3 instructions: Table 624. Miscellaneous instructions UM10360 User manual Mnemonic Brief description See BKPT Breakpoint Section 34.2.10.1 CPSID Change Processor State, Disable Interrupts Section 34.2.10.2 CPSIE Change Processor State, Enable Interrupts Section 34.2.10.2 DMB Data Memory Barrier Section 34.2.10.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.10.1 BKPT Breakpoint. 34.2.10.1.1 Syntax BKPT #imm where: imm is an expression evaluating to an integer in the range 0-255 (8-bit value). 34.2.10.1.2 Operation The BKPT instruction causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. imm is ignored by the processor.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.10.2 CPS Change Processor State. 34.2.10.2.1 Syntax CPSeffect iflags where: effect is one of: IE Clears the special purpose register. ID Sets the special purpose register iflags is a sequence of one or more flags: i Set or clear PRIMASK. f Set or clear FAULTMASK. 34.2.10.2.2 Operation CPS changes the PRIMASK and FAULTMASK special register values. See Section 34.3.1.3.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.10.3 DMB Data Memory Barrier. 34.2.10.3.1 Syntax DMB{cond} where: cond is an optional condition code, see Section 34.2.3.7 “Conditional execution”. 34.2.10.3.2 Operation DMB acts as a data memory barrier. It ensures that all explicit memory accesses that appear, in program order, before the DMB instruction are completed before any explicit memory accesses that appear, in program order, after the DMB instruction.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.10.4 DSB Data Synchronization Barrier. 34.2.10.4.1 Syntax DSB{cond} where: cond is an optional condition code, see Section 34.2.3.7 “Conditional execution”. 34.2.10.4.2 Operation DSB acts as a special data synchronization memory barrier. Instructions that come after the DSB, in program order, do not execute until the DSB instruction completes. The DSB instruction completes when all explicit memory accesses before it complete.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.10.5 ISB Instruction Synchronization Barrier. 34.2.10.5.1 Syntax ISB{cond} where: cond is an optional condition code, see Section 34.2.3.7 “Conditional execution”. 34.2.10.5.2 Operation ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor, so that all instructions following the ISB are fetched from cache or memory again, after the ISB instruction has been completed. 34.2.10.5.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.10.6 MRS Move the contents of a special register to a general-purpose register. 34.2.10.6.1 Syntax MRS{cond} Rd, spec_reg where: cond is an optional condition code, see Section 34.2.3.7 “Conditional execution”. Rd is the destination register. spec_reg can be any of: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR, MSP, PSP, PRIMASK, BASEPRI, BASEPRI_MAX, FAULTMASK, or CONTROL. 34.2.10.6.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.10.7 MSR Move the contents of a general-purpose register into the specified special register. 34.2.10.7.1 Syntax MSR{cond} spec_reg, Rn where: cond is an optional condition code, see Section 34.2.3.7 “Conditional execution”. Rn is the source register. spec_reg can be any of: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR, MSP, PSP, PRIMASK, BASEPRI, BASEPRI_MAX, FAULTMASK, or CONTROL. 34.2.10.7.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.10.8 NOP No Operation. 34.2.10.8.1 Syntax NOP{cond} where: cond is an optional condition code, see Section 34.2.3.7 “Conditional execution”. 34.2.10.8.2 Operation NOP does nothing. NOP is not necessarily a time-consuming NOP. The processor might remove it from the pipeline before it reaches the execution stage. Use NOP for padding, for example to place the following instruction on a 64-bit boundary. 34.2.10.8.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.10.9 SEV Send Event. 34.2.10.9.1 Syntax SEV{cond} where: cond is an optional condition code, see Section 34.2.3.7 “Conditional execution”. 34.2.10.9.2 Operation SEV is a hint instruction that causes an event to be signaled to all processors within a multiprocessor system. It also sets the local event register to 1, see Section 34.3.5 “Power management”. 34.2.10.9.3 Condition flags This instruction does not change the flags.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.10.10 SVC Supervisor Call. 34.2.10.10.1 Syntax SVC{cond} #imm where: cond is an optional condition code, see Section 34.2.3.7 “Conditional execution”. imm is an expression evaluating to an integer in the range 0-255 (8-bit value). 34.2.10.10.2 Operation The SVC instruction causes the SVC exception. imm is ignored by the processor.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.10.11 WFE Wait For Event. 34.2.10.11.1 Syntax WFE{cond} where: cond is an optional condition code, see Section 34.2.3.7 “Conditional execution” 34.2.10.11.2 Operation WFE is a hint instruction.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.10.12 WFI Wait for Interrupt. 34.2.10.12.1 Syntax WFI{cond} where: cond is an optional condition code, see Section 34.2.3.7 “Conditional execution”. 34.2.10.12.2 Operation WFI is a hint instruction that suspends execution until one of the following events occurs: • an exception • a Debug Entry request, regardless of whether Debug is enabled. 34.2.10.12.3 Condition flags This instruction does not change the flags. 34.2.10.12.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.3 ARM Cortex-M3 User Guide: Processor 34.3.1 Programmers model This section describes the Cortex-M3 programmers model. In addition to the individual core register descriptions, it contains information about the processor modes and privilege levels for software execution and stacks. 34.3.1.1 Processor mode and privilege levels for software execution The processor modes are: • Thread mode Used to execute application software.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 625. Summary of processor mode, execution privilege level, and stack use options Processor mode Used to execute Privilege level for software execution Stack used Thread Applications Privileged or unprivileged [1] Main stack or process stack [1] Handler Exception handlers Always privileged Main stack [1] See Table 634. 34.3.1.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 626. Core register set summary Name Type [1] Required privilege [2] Reset value Description EPSR RO Privileged 0x01000000 Table 630 PRIMASK RW Privileged 0x00000000 Table 631 FAULTMASK RW Privileged 0x00000000 Table 632 BASEPRI RW Privileged 0x00000000 Table 633 CONTROL RW Privileged 0x00000000 Table 634 [1] Describes access type during program execution in thread mode and Handler mode.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 31 30 29 28 27 26 25 24 23 16 15 APSR N Z C V Q 10 9 8 Reserved IPSR Reserved EPSR Reserved 0 ICI/IT T ISR_NUMBER Reserved ICI/IT Reserved The PSR bit assignments are: 31 30 29 28 27 26 25 24 23 16 15 N Z C V Q ICI/IT T Reserved 10 9 8 ICI/IT 0 ISR_NUMBER Reserved Access these registers individually or as a combination of any two or all three registers, using the register name as an argument to the MSR or MRS inst
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 628. APSR bit assignments Bits Name [31] N Function Negative or less than flag: 0 = operation result was positive, zero, greater than, or equal 1 = operation result was negative or less than. [30] Z Zero flag: 0 = operation result was not zero 1 = operation result was zero.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 629. IPSR bit assignments Bits Name Function [31:9] - Reserved [8:0] ISR_NUMBER This is the number of the current exception: 0 = Thread mode 1 = Reserved 2 = NMI 3 = Hard fault 4 = Memory management fault 5 = Bus fault 6 = Usage fault 7-10 = Reserved 11 = SVCall 12 = Reserved for Debug 13 = Reserved 14 = PendSV 15 = SysTick 16 = IRQ0 17 = IRQ1, first device specific interrupt . .
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Interruptible-continuable instructions: When an interrupt occurs during the execution of an LDM or STM instruction, the processor: After servicing the interrupt, the processor: • stops the load multiple or store multiple instruction operation temporarily. • stores the next register operand in the multiple operation to EPSR bits[15:12]. • returns to the register pointed to by bits[15:12].
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 633. BASEPRI register bit assignments Bits Name Function [31:8] - Reserved [7:0] BASEPRI [1] Priority mask bits: 0x0000 = no effect Nonzero = defines the base priority for exception processing. The processor does not process any exception with a priority value greater than or equal to BASEPRI. [1] 34.3.1.3.7 This field is similar to the priority fields in the interrupt priority registers.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide The NVIC registers control interrupt handling. See Section 34.4.2 “Nested Vectored Interrupt Controller” for more information. 34.3.1.5 Data types The processor: • supports the following data types: – 32-bit words – 16-bit halfwords – 8-bit bytes • supports 64-bit data transfer instructions. • manages all data memory accesses as little-endian. See Section 34.3.2.1 for more information. 34.3.1.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide • Section 34.4.2.10.1 “NVIC programming hints”. UM10360 User manual All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 August 2010 © NXP B.V. 2010. All rights reserved.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.3.2 Memory model This section describes the processor memory map, the behavior of memory accesses, and the bit-banding features. The processor has a fixed memory map that provides up to 4GB of addressable memory. The memory map is: 0xFFFFFFFF Vendor-specific memory 511MB 0xE0100000 0xE00FFFFF Private peripheral 1.0MB bus 0xE0000000 0xDFFFFFFF External device 1.0GB 0xA0000000 0x9FFFFFFF External RAM 0x43FFFFFF 1.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide • Normal: The processor can re-order transactions for efficiency, or perform speculative reads. • Device: The processor preserves transaction order relative to other transactions to Device or Strongly-ordered memory. • Strongly-ordered: The processor preserves transaction order relative to all other transactions.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide ‘<‘ means that accesses are observed in program order, that is, A1 is always observed before A2. 34.3.2.3 Behavior of memory accesses The behavior of accesses to each region in the memory map is: Table 635. Memory access behavior Address range Memory region Memory type XN Description 0x00000000 0x1FFFFFFF Code Normal [1] - Executable region for program code. You can also put data here.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide • DMB The Data Memory Barrier (DMB) instruction ensures that outstanding memory transactions complete before subsequent memory transactions. See Section 34.2.10.3 “DMB”. • DSB The Data Synchronization Barrier (DSB) instruction ensures that outstanding memory transactions complete before subsequent instructions execute. See Section 34.2.10.4 “DSB”.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide The memory map has two 32MB alias regions that map to two 1MB bit-band regions: • accesses to the 32MB SRAM alias region map to the 1MB SRAM bit-band region, as shown in Table 636 • accesses to the 32MB peripheral alias region map to the 1MB peripheral bit-band region, as shown in Table 637. Table 636.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide • The alias word at 0x23FFFFFC maps to bit[7] of the bit-band byte at 0x200FFFFF: 0x23FFFFFC = 0x22000000 + (0xFFFFF*32) + (7*4). • The alias word at 0x22000000 maps to bit[0] of the bit-band byte at 0x20000000: 0x22000000 = 0x22000000 + (0*32) + (0 *4). • The alias word at 0x2200001C maps to bit[7] of the bit-band byte at 0x20000000: 0x2200001C = 0x22000000+ (0*32) + (7*4).
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.3.2.6 Memory endianness The processor views memory as a linear collection of bytes numbered in ascending order from zero. For example, bytes 0-3 hold the first stored word, and bytes 4-7 hold the second stored word. Section 34.3.2.6.1 describes how words of data are stored in memory. 34.3.2.6.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide To perform a guaranteed read-modify-write of a memory location, software must: 1. Use a Load-Exclusive instruction to read the value of the location. 2. Update the value, as required. 3. Use a Store-Exclusive instruction to attempt to write the new value back to the memory location, and tests the returned status bit. If this bit is: – 0: The read-modify-write completed successfully, – 1: No write was performed.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.3.3 Exception model This section describes the exception model. 34.3.3.1 Exception states Each exception is in one of the following states: • Inactive The exception is not active and not pending. • Pending The exception is waiting to be serviced by the processor. An interrupt request from a peripheral or from software can change the state of the corresponding interrupt to pending.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide A memory management fault is an exception that occurs because of a memory protection related fault. The MPU or the fixed memory protection constraints determines this fault, for both instruction and data memory transactions. This fault is used to abort instruction accesses to Execute Never (XN) memory regions, even if the MPU is disabled.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 639.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.3.3.4 Vector table The vector table contains the reset value of the stack pointer, and the start addresses, also called exception vectors, for all exception handlers. Figure 147 shows the order of the exception vectors in the vector table. The least-significant bit of each vector must be 1, indicating that the exception handler is Thumb code. Note that the upper limit of the IRQ number is device dependent.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide • Section 34.4.3.9 “System Handler Priority Registers” • Section 34.4.2.7 “Interrupt Priority Registers”. Remark: Configurable priority values are in the range 0 to 31. This means that the Reset, Hard fault, and NMI exceptions, with fixed negative priority values, always have higher priority than any other exception.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide – there is no pending exception with sufficient priority to be serviced – the completed exception handler was not handling a late-arriving exception. The processor pops the stack and restores the processor state to the state it had before the interrupt occurred. See Section 34.3.3.7.2 for more information. • Tail-chaining This mechanism speeds up exception servicing.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide The stack frame includes the return address. This is the address of the next instruction in the interrupted program. This value is restored to the PC at exception return so that the interrupted program resumes. In parallel to the stacking operation, the processor performs a vector fetch that reads the exception handler start address from the vector table. When stacking is complete, the processor starts executing the exception handler.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 640. Exception return behavior EXC_RETURN[3:0] Description b1001 Return to Thread mode. Exception return gets state from MSP. Execution uses MSP after return. b1101 Return to Thread mode. Exception return gets state from PSP. Execution uses PSP after return. b1X11 UM10360 User manual Reserved. All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 August 2010 © NXP B.V. 2010.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.3.4 Fault handling Faults are a subset of the exceptions, see Section 34.3.3.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.3.4.2 Fault escalation and hard faults All faults exceptions except for hard fault have configurable exception priority, see Section 34.4.3.9 “System Handler Priority Registers”. Software can disable execution of the handlers for these faults, see Section 34.4.3.10 “System Handler Control and State Register”.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.3.4.4 Lockup The processor enters a lockup state if a hard fault occurs when executing the NMI or hard fault handlers. When the processor is in lockup state it does not execute any instructions. The processor remains in lockup state until either: • it is reset • an NMI occurs. Remark: If lockup state occurs from the NMI handler a subsequent NMI does not cause the processor to leave lockup state.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.3.5 Power management Note: NXP devices based on the Cortex-M3 processor, including the LPC17xx, support additional reduced power modes. See Section 4.8 “Power control” for information on all available reduced power modes. The Cortex-M3 processor sleep modes reduce power consumption: • Sleep mode stops the processor clock • Deep sleep mode stops the system clock and switches off the PLL and flash memory.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.3.5.1.3 Sleep-on-exit If the SLEEPONEXIT bit of the SCR is set to 1, when the processor completes the execution of an exception handler it returns to Thread mode and immediately enters sleep mode. Use this mechanism in applications that only require the processor to run when an exception occurs. 34.3.5.2 Wakeup from sleep mode The conditions for the processor to wakeup depend on the mechanism that cause it to enter sleep mode. 34.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Remark: If the processor detects a connection to a debugger it disables the WIC. 34.3.5.4 Power management programming hints ANSI C cannot directly generate the WFI and WFE instructions. The CMSIS provides the following intrinsic functions for these instructions: void __WFE(void) // Wait for Event void __WFE(void) // Wait for Interrupt UM10360 User manual All information provided in this document is subject to legal disclaimers.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.4 ARM Cortex-M3 User Guide: Peripherals 34.4.1 About the Cortex-M3 peripherals The address map of the Private peripheral bus (PPB) is: Table 643.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.4.2 Nested Vectored Interrupt Controller This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it uses. The NVIC supports: • Up to 112 interrupts. The number of interrupts implemented is device dependent. • A programmable priority level of 0 to 31 for each interrupt. A higher level corresponds to a lower priority, so level 0 is the highest interrupt priority.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide The CMSIS provides thread-safe code that gives atomic access to the Interrupt Priority Registers. For more information see the description of the NVIC_SetPriority function in Section 34.4.2.10.1 “NVIC programming hints”. Table 645 shows how the interrupts, or IRQ numbers, map onto the interrupt registers and corresponding CMSIS variables that have one bit per interrupt. Table 645.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 647. ICER bit assignments Bits Name Function [31:0] CLRENA Interrupt clear-enable bits. Write: 0 = no effect 1 = disable interrupt. Read: 0 = interrupt disabled 1 = interrupt enabled. 34.4.2.4 Interrupt Set-pending Registers The ISPR0-ISPR3 registers force interrupts into the pending state, and show which interrupts are pending.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 649. ICPR bit assignments Bits Name Function [31:0] CLRPEND Interrupt clear-pending bits. Write: 0 = no effect 1 = removes pending state an interrupt. Read: 0 = interrupt is not pending 1 = interrupt is pending. Remark: Writing 1 to an ICPR bit does not affect the active state of the corresponding interrupt. 34.4.2.6 Interrupt Active Bit Registers The IABR0-IABR3 registers indicate which interrupts are active.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 651. IPR bit assignments Bits Name [31:24] Priority, byte offset 3 Each priority field holds a priority value, 0-31. The lower the Priority, byte offset 2 value, the greater the priority of the corresponding interrupt. The processor implements only bits[7:3] of each field, bits[2:0] Priority, byte offset 1 read as zero and ignore writes.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide When the processor enters the ISR, it automatically removes the pending state from the interrupt, see Section 34.4.2.9.1. For a level-sensitive interrupt, if the signal is not deasserted before the processor returns from the ISR, the interrupt becomes pending again, and the processor must execute its ISR again. This means that the peripheral can hold the interrupt signal asserted until it no longer needs servicing. 34.4.2.9.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.4.2.10.1 NVIC programming hints Software uses the CPSIE I and CPSID I instructions to enable and disable interrupts. The CMSIS provides the following intrinsic functions for these instructions: void __disable_irq(void) // Disable Interrupts void __enable_irq(void) // Enable Interrupts In addition, the CMSIS provides a number of functions for NVIC control, including: Table 653.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.4.3 System control block The System control block (SCB) provides system implementation information, and system control. This includes configuration, control, and reporting of the system exceptions. The system control block registers are: Table 654.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 655. ACTLR bit assignments Bits Name Function [31:3] - Reserved [2] DISFOLD When set to 1, disables IT folding. see Section 34.4.3.2.1 for more information. [1] DISDEFWBUF When set to 1, disables write buffer use during default memory map accesses.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide – whether there are preempted active exceptions – the exception number of the highest priority pending exception – whether any interrupts are pending. See the register summary in Table 654, and the Type descriptions in Table 657, for the ICSR attributes. The bit assignments are shown in Table 657. Table 657. ICSR bit assignments Bits Name Type Function [31] NMIPENDSET RW NMI set-pending bit.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 657. ICSR bit assignments Bits Name Type Function [25] PENDSTCLR WO SysTick exception clear-pending bit. Write: 0 = no effect 1 = removes the pending state from the SysTick exception. This bit is WO. On a register read its value is Unknown. [24] - - Reserved. [23] Reserved for Debug use RO This bit is reserved for Debug use and reads-as-zero when the processor is not in Debug.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 658. VTOR bit assignments Bits Name Function [31:30] - Reserved. [29:8] TBLOFF Vector table base offset field. It contains bits[29:8] of the offset of the table base from the bottom of the memory map. Remark: Bit[29] determines whether the vector table is in the code or SRAM memory region: Bit[29] is sometimes called the TBLBASE bit. • • [7:0] - 0 = code 1 = SRAM. Reserved.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 659. AIRCR bit assignments Bits Name Type Function [2] SYSRESETREQ WO System reset request: 0 = no system reset request 1 = asserts a signal to the outer system that requests a reset. This is intended to force a large system reset of all major components except for debug. Note: support for SYSRESETREQ is not included in LPC17xx devices. This bit reads as 0. 34.4.3.6.1 [1] VECTCLRACTIVE WO Reserved for Debug use.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 661. SCR bit assignments Bits Name Function [31:5] - Reserved. [4] SEVONPEND Send Event on Pending bit: 0 = only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded 1 = enabled events and all interrupts, including disabled interrupts, can wakeup the processor. When an event or interrupt enters pending state, the event signal wakes up the processor from WFE.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 662. CCR bit assignments Bits Name Function [31:10] - Reserved. [9] STKALIGN Indicates stack alignment on exception entry: 0 = 4-byte aligned 1 = 8-byte aligned. On exception entry, the processor uses bit[9] of the stacked PSR to indicate the stack alignment. On return from the exception it uses this stacked bit to restore the correct stack alignment.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 663. System fault handler priority fields Handler Field Register description Memory management fault PRI_4 Table 664 Bus fault PRI_5 Usage fault PRI_6 SVCall PRI_11 Table 665 PendSV PRI_14 Table 666 SysTick PRI_15 Each PRI_N field is 8 bits wide, but the processor implements only bits[7:3] of each field, and bits[2:0] read as zero and ignore writes. 34.4.3.9.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 667.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.4.3.11 Configurable Fault Status Register The CFSR indicates the cause of a memory management fault, bus fault, or usage fault. See the register summary in Table 654 for its attributes.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 668. MMFSR bit assignments Bits Name Function [3] MUNSTKERR Memory manager fault on unstacking for a return from exception: 0 = no unstacking fault 1 = unstack for an exception return has caused one or more access violations. This fault is chained to the handler. This means that when this bit is 1, the original return stack is still present.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 669. BFSR bit assignments Bits Name Function [4] STKERR Bus fault on stacking for exception entry: 0 = no stacking fault 1 = stacking for an exception entry has caused one or more bus faults. When the processor sets this bit to 1, the SP is still adjusted but the values in the context area on the stack might be incorrect. The processor does not write a fault address to the BFAR.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 670. UFSR bit assignments Bits Name Function [15:10] - Reserved. [9] DIVBYZERO Divide by zero usage fault: 0 = no divide by zero fault, or divide by zero trapping not enabled 1 = the processor has executed an SDIV or UDIV instruction with a divisor of 0. When the processor sets this bit to 1, the PC value stacked for the exception return points to the instruction that performed the divide by zero.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.4.3.12 Hard Fault Status Register The HFSR gives information about events that activate the hard fault handler. See the register summary in Table 654 for its attributes. This register is read, write to clear. This means that bits in the register read normally, but writing 1 to any bit clears that bit to 0. The bit assignments are shown in Table 671. Table 671.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 673. BFAR bit assignments Bits Name Function [31:0] ADDRESS When the BFARVALID bit of the BFSR is set to 1, this field holds the address of the location that generated the bus fault When an unaligned access faults the address in the BFAR is the one requested by the instruction, even if it is not the address of the fault. Flags in the BFSR indicate the cause of the fault, and whether the value in the BFAR is valid.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.4.4 System timer, SysTick The processor has a 24-bit system timer, SysTick, that counts down from the reload value to zero, reloads (wraps to) the value in the LOAD register on the next clock edge, then counts down on subsequent clocks. Note: refer to the separate chapter in the LPC17xx User Manual Section 23.1 for device specific information on the System Timer.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.4.4.2 SysTick Reload Value Register The LOAD register specifies the start value to load into the VAL register. See the register summary in Table 674 for its attributes. The bit assignments are shown in Table 676. Table 676. LOAD register bit assignments 34.4.4.2.1 Bits Name Function [31:24] - Reserved. [23:0] RELOAD Value to load into the VAL register when the counter is enabled and when it reaches 0, see Section 34.4.4.2.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide If a different frequency is used than that intended by the factory preset value, calculate the calibration value required from the frequency of the processor clock or external clock. 34.4.4.5 SysTick design hints and tips The SysTick counter runs on the processor clock. If this clock signal is stopped for low power mode while the SysTick counter is running from it, the SysTick counter will stop.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.4.5 Memory protection unit This section describes the Memory protection unit (MPU). The MPU divides the memory map into a number of regions, and defines the location, size, access permissions, and memory attributes of each region. It supports: • independent attribute settings for each region • overlapping regions • export of memory attributes to the system. The memory attributes affect the behavior of memory accesses to the region.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 679. Memory attributes summary Memory type Normal Shareability Other attributes Description Non-shared - Memory-mapped peripherals that only a single processor uses. Shared Non-cacheable Write-through Cacheable Write-back Cacheable Normal memory that is shared between several processors. Non-shared Non-cacheable Write-through Cacheable Write-back Cacheable Normal memory that only a single processor uses.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 681. TYPE register bit assignments Bits Name Function [15:8] DREGION Indicates the number of supported MPU data regions: [7:0] - Reserved. [0] SEPARATE Indicates support for unified or separate instruction and date memory maps: 0x08 = Eight MPU regions. 0 = unified. 34.4.5.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide • For privileged accesses, the default memory map is as described in Section 34.3.2 “Memory model”. Any access by privileged software that does not address an enabled memory region behaves as defined by the default memory map. • Any access by unprivileged software that does not address an enabled memory region causes a memory management fault.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 684. RBAR bit assignments [31:N] ADDR Region base address field. The value of N depends on the region size. For more information see Section 34.4.5.4.1. [(N-1):5] - Reserved.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 685. RASR bit assignments Bits Name Function [31:29] - Reserved. [28] XN Instruction access disable bit: 0 = instruction fetches enabled 1 = instruction fetches disabled. [27] - Reserved. [26:24] AP Access permission field, see Table 689. [23:22] - Reserved. [21:19, 17, 16] TEX, C, B Memory access attributes, see Table 687. [18] S Shareable bit, see Table 687. [15:8] SRD Subregion disable bits.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.4.5.6 MPU access permission attributes This section describes the MPU access permission attributes. The access permission bits, TEX, C, B, S, AP, and XN, of the RASR, control access to the corresponding memory region. If an access is made to an area of memory without the required permissions, then the MPU generates a permission fault. Table 687 shows the encodings for the TEX, C, B, and S access permission bits. Table 687.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 689.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide ; R3 = attributes ; R4 = address LDR R0,=MPU_RNR ; 0xE000ED98, MPU region number register STR R1, [R0, #0x0] ; Region Number BIC R2, R2, #1 ; Disable STRH R2, [R0, #0x8] ; Region Size and Enable STR R4, [R0, #0x4] ; Region Base Address STRH R3, [R0, #0xA] ; Region Attribute ORR R2, #1 ; Enable STRH R2, [R0, #0x8] ; Region Size and Enable Software must use memory barrier instructions: • before MPU setup if there might b
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Use an STM instruction to optimize this: ; R1 = region number ; R2 = address ; R3 = size, attributes in one LDR R0, =MPU_RNR ; 0xE000ED98, MPU region number register STM R0, {R1-R3} ; Region Number, address, attribute, size and enable You can do this in two words for pre-packed information. This means that the RBAR contains the required region number and had the VALID bit set to 1, see Table 684.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Region 2, with subregions Region 1 Base address of both regions Offset from base address 512KB 448KB 384KB 320KB 256KB 192KB 128KB Disabled subregion 64KB Disabled subregion 0 34.4.5.9 MPU design hints and tips To avoid unexpected behavior, disable the interrupts before updating the attributes of a region that the interrupt handlers might access.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.5 ARM Cortex-M3 User Guide: Glossary Abort — A mechanism that indicates to a processor that the value associated with a memory access is invalid. An abort can be caused by the external or internal memory system as a result of attempting to access invalid instruction or data memory. Aligned — A data item stored at an address that is divisible by the number of bytes that defines the data size is said to be aligned.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Condition field — A four-bit field in an instruction that specifies a condition under which the instruction can execute. Context — The environment that each process operates in for a multitasking operating system. In ARM processors, this is limited to mean the physical address range that it can access in memory and the associated memory access permissions. Coprocessor — A processor that supplements the main processor.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Index register — In some load and store instruction descriptions, the value of this register is used as an offset to be added to or subtracted from the base register value to form the address that is sent to memory. Some addressing modes optionally enable the index register value to be shifted prior to the addition or subtraction. See also Base register.
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UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Should Be Zero or Preserved (SBZP) — Write as 0, or all 0s for bit fields, by software, or preserved by writing the same value back that has been previously read from the same field on the same processor. Thread-safe — In a multi-tasking environment, thread-safe functions use safeguard mechanisms when accessing shared resources, to ensure correct operation without the risk of shared access conflicts.
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UM10360 Chapter 35: Supplementary information Rev. 2 — 19 August 2010 User manual 35.1 Abbreviations Table 691.
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UM10360 NXP Semiconductors Chapter 35: Supplementary information 35.2 Legal information 35.2.1 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 35.2.
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UM10360 NXP Semiconductors Chapter 35: Supplementary information 35.3 Tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Ordering information . . . . . . . . . . . . . . . . . . . . .
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UM10360 NXP Semiconductors Chapter 35: Supplementary information Table 67. Interrupt Priority Register 5 (IPR5 - 0xE000 E414) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 Table 68. Interrupt Priority Register 6 (IPR6 - 0xE000 E418) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 Table 69. Interrupt Priority Register 7 (IPR7 - 0xE000 E41C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 Table 70. Interrupt Priority Register 8 (IPR8 - 0xE000 E420) . .
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UM10360 NXP Semiconductors Chapter 35: Supplementary information Table 122. GPIO Interrupt Clear register for port 0 (IO0IntClr - 0x4002 808C)) bit description . . . . . . . . . . .138 Table 123. GPIO Interrupt Clear register for port 0 (IO2IntClr - 0x4002 80AC) bit description . . . . . . . . . . . .139 Table 124. Ethernet acronyms, abbreviations, and definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 Table 125. Example PHY Devices. . . . . . . . . . . . . . . . . .147 Table 126.
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UM10360 NXP Semiconductors Chapter 35: Supplementary information Table 179. Receive status information word . . . . . . . . . .174 Table 180. Transmit descriptor fields. . . . . . . . . . . . . . . .176 Table 181. Transmit descriptor control word . . . . . . . . . .176 Table 182. Transmit status fields . . . . . . . . . . . . . . . . . . .176 Table 183. Transmit status information word . . . . . . . . . .177 Table 184. USB related acronyms, abbreviations, and definitions used in this chapter . . . . . .
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UM10360 NXP Semiconductors Chapter 35: Supplementary information (USBDMAIntEn - address 0x5000 C294) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .239 Table 232. USB End of Transfer Interrupt Status register (USBEoTIntSt - address 0x5000 C2A0s) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .239 Table 233. USB End of Transfer Interrupt Clear register (USBEoTIntClr - address 0x5000 C2A4) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .
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UM10360 NXP Semiconductors Chapter 35: Supplementary information Table 285: UARTn Fractional Divider Register (U0FDR address 0x4000 C028, U2FDR - 0x4009 8028, U3FDR - 0x4009 C028) bit description. . . . . .312 Table 286. Fractional Divider setting look-up table . . . . .315 Table 287: UARTn Transmit Enable Register (U0TER address 0x4000 C030, U2TER - 0x4009 8030, U3TER - 0x4009 C030) bit description . . . . . .316 Table 288: UART1 Pin Description . . . . . . . . . . . . . . . . .
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UM10360 NXP Semiconductors Chapter 35: Supplementary information Table 336. CAN Wake-up Flags register (CANWAKEFLAGS - address 0x400F C114) bit description . . . . .370 Table 337. Central Transit Status Register (CANTxSR address 0x4004 0000) bit description. . . . . . .372 Table 338. Central Receive Status Register (CANRxSR address 0x4004 0004) bit description. . . . . . .372 Table 339. Central Miscellaneous Status Register (CANMSR - address 0x4004 0008) bit description . . . . .373 Table 340.
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UM10360 NXP Semiconductors Chapter 35: Supplementary information I2C1MMCTRL- 0x4005 C01C; I2C2, I2C2MMCTRL- 0x400A 001C) bit description 444 Table 389. I2C Data buffer register (I2DATA_BUFFER: I2C0, I2CDATA_BUFFER - 0x4001 C02C; I2C1, I2C1DATA_BUFFER- 0x4005 C02C; I2C2, I2C2DATA_BUFFER- 0x400A 002C) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .446 Table 390.
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UM10360 NXP Semiconductors Chapter 35: Supplementary information Table 446: PWM Interrupt Register (PWM1IR - address 0x4001 8000) bit description . . . . . . . . . . . . .515 Table 447. PWM Timer Control Register (PWM1TCR address 0x4001 8004) bit description. . . . . . .516 Table 448. PWM Count control Register (PWM1CTCR address 0x4001 8070) bit description. . . . . . .516 Table 449: Match Control Register (PWM1MCR - address 0x4001 8014) bit description . . . . . . . . . . . . .
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UM10360 NXP Semiconductors Chapter 35: Supplementary information Table 502: QEI Interrupt Clear register (QEICLR 0x400B CFE8) bit description . . . . . . . . . . . . .555 Table 503: QEI Interrupt Enable register (QEIIE - address 0x400B CFE4) bit description . . . . . . . . . . . . .555 Table 504: QEI Interrupt Enable Set register (QEIIES address 0x400B CFDC) bit description . . . . .556 Table 505: QEI Interrupt Enable Clear register (QEIIEC address 0x400B CFD8) bit description . . . . . .557 Table 506.
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UM10360 NXP Semiconductors Chapter 35: Supplementary information Table 566. DMA request signal usage . . . . . . . . . . . . . .609 Table 567. Sectors in a LPC17xx device . . . . . . . . . . . . .620 Table 568. Code Read Protection options[1] . . . . . . . . . .621 Table 569. Code Read Protection hardware/software interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . .622 Table 570. ISP command summary. . . . . . . . . . . . . . . . .623 Table 571. ISP Unlock command . . . . . . . . . . . . .
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UM10360 NXP Semiconductors Chapter 35: Supplementary information Table 659. AIRCR bit assignments . . . . . . . . . . . . . . . . .771 Table 660. Priority grouping. . . . . . . . . . . . . . . . . . . . . . .772 Table 661. SCR bit assignments . . . . . . . . . . . . . . . . . . .773 Table 662. CCR bit assignments . . . . . . . . . . . . . . . . . . .774 Table 663. System fault handler priority fields . . . . . . . . .775 Table 664. SHPR1 register bit assignments . . . . . . . . . .775 Table 665.
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UM10360 NXP Semiconductors Chapter 35: Supplementary information 35.4 Figures Fig 1. Fig 2. Fig 3. Fig 4. Fig 5. Fig 6. Fig 7. Fig 8. Fig 9. Fig 10. Fig 11. Fig 12. Fig 13. Fig 14. Fig 15. Fig 16. Fig 17. Fig 18. Fig 19. Fig 20. Fig 21. Fig 22. Fig 23. Fig 24. Fig 25. Fig 26. Fig 27. Fig 28. Fig 29. Fig 30. Fig 31. Fig 32. Fig 33. Fig 34. Fig 35. Fig 36. Fig 37. Fig 38. Fig 39. Fig 40. Fig 41. Fig 42. Fig 43. Fig 44. Fig 45. Fig 46. Fig 47. Fig 48. Fig 49. LPC1768 simplified block diagram. . . . . . .
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UM10360 NXP Semiconductors Chapter 35: Supplementary information Fig 88. Fig 89. Fig 90. Fig 91. Fig 92. Fig 93. Format of Slave Receiver mode . . . . . . . . . . . .434 Format of Slave Transmitter mode . . . . . . . . . .434 I2C serial interface block diagram . . . . . . . . . . .435 Arbitration procedure . . . . . . . . . . . . . . . . . . . . .437 Serial clock synchronization. . . . . . . . . . . . . . . .437 Format and states in the Master Transmitter mode . . . . . . . . . . . . . . . . . . . . . .
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UM10360 NXP Semiconductors Chapter 35: Supplementary information 35.5 Contents Chapter 1: LPC17xx Introductory information 1.1 1.2 1.3 1.4 1.4.1 1.5 1.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering information . . . . . . . . . . . . . . . . . . . . . Part options summary. . . . . . . . . . . . . . . . . . . .
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UM10360 NXP Semiconductors Chapter 35: Supplementary information Example 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Example 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 4.5.13 PLL0 setup sequence . . . . . . . . . . . . . . . . . . . 46 4.6 PLL1 (Phase Locked Loop 1) . . . . . . . . . . . . . 47 4.6.1 PLL1 register description . . . . . . . . . . . . . . . . 47 4.6.2 PLL1 Control register (PLL1CON - 0x400F C0A0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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UM10360 NXP Semiconductors Chapter 35: Supplementary information 6.5.14 6.5.15 6.5.16 6.5.17 Interrupt Priority Register 3 (IPR3 - 0xE000 E40C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Priority Register 4 (IPR4 - 0xE000 E410) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Priority Register 5 (IPR5 - 0xE000 E414) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Priority Register 6 (IPR6 - 0xE000 E418) . . . . . . . . . . . . .
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UM10360 NXP Semiconductors Chapter 35: Supplementary information 9.5.4 9.5.5 9.5.6 9.5.6.1 9.5.6.2 9.5.6.3 9.5.6.4 9.5.6.5 GPIO port Pin value register FIOxPIN (FIO0PIN to FIO4PIN- 0x2009 C014 to 0x2009 C094) . . 127 Fast GPIO port Mask register FIOxMASK (FIO0MASK to FIO4MASK - 0x2009 C010 to 0x2009 C090) . . . . . . . . . . . . . . . . . . . . . . . . 129 GPIO interrupt registers . . . . . . . . . . . . . . . . 131 GPIO overall Interrupt Status register (IOIntStatus - 0x4002 8080) . . . . . . . . . .
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UM10360 NXP Semiconductors Chapter 35: Supplementary information 10.12.7 Receive Consume Index Register (RxConsumeIndex - 0x5000 0118) . . . . . . . . 160 10.12.8 Transmit Descriptor Base Address Register (TxDescriptor - 0x5000 011C). . . . . . . . . . . . 161 10.12.9 Transmit Status Base Address Register (TxStatus - 0x5000 0120) . . . . . . . . . . . . . . . . . . . . . . . 161 10.12.10 Transmit Number of Descriptors Register (TxDescriptorNumber - 0x5000 0124) . . . . . 161 10.12.
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UM10360 NXP Semiconductors Chapter 35: Supplementary information 11.9.1 Power requirements . . . . . . . . . . . . . . . . . . . 218 11.9.2 Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 11.9.3 Power management support . . . . . . . . . . . . 219 11.9.4 Remote wake-up . . . . . . . . . . . . . . . . . . . . . 220 11.10 Register description . . . . . . . . . . . . . . . . . . . 220 11.10.1 Clock control registers . . . . . . . . . . . . . . . . . 221 11.10.1.
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UM10360 NXP Semiconductors Chapter 35: Supplementary information 11.12 Serial interface engine command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 11.12.1 Set Address (Command: 0xD0, Data: write 1 byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 11.12.2 Configure Device (Command: 0xD8, Data: write 1 byte). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 11.12.3 Set Mode (Command: 0xF3, Data: write 1 byte). . . . . . . . .
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UM10360 NXP Semiconductors Chapter 35: Supplementary information 12.4.2 12.4.2.1 Software interface. . . . . . . . . . . . . . . . . . . . . 271 Register map . . . . . . . . . . . . . . . . . . . . . . . . 271 12.4.2.2 USB Host Register Definitions . . . . . . . . . . . 272 Chapter 13: LPC17xx USB OTG 13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.7.1 13.7.2 13.7.3 13.8 13.8.1 13.8.2 13.8.3 13.8.4 13.8.5 13.8.6 13.8.7 13.8.8 13.8.9 How to read this chapter . . . . . . . . . . . . . . . .
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UM10360 NXP Semiconductors Chapter 35: Supplementary information 14.4.6 14.4.6.1 14.4.7 14.4.8 14.4.9 14.4.10 UARTn FIFO Control Register (U0FCR 0x4000 C008, U2FCR - 0x4009 8008, U3FCR 0x4009 C008) . . . . . . . . . . . . . . . . . . . . . . . . 305 DMA Operation . . . . . . . . . . . . . . . . . . . . . . . 305 UART receiver DMA . . . . . . . . . . . . . . . . . . . .305 UART transmitter DMA . . . . . . . . . . . . . . . . . .
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UM10360 NXP Semiconductors Chapter 35: Supplementary information 15.5 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 341 Chapter 16: LPC17xx CAN1/2 16.1 Basic configuration . . . . . . . . . . . . . . . . . . . . 343 16.2 CAN controllers . . . . . . . . . . . . . . . . . . . . . . . 343 16.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 16.3.1 General CAN features . . . . . . . . . . . . . . . . . 343 16.3.2 CAN controller features . . . . . . . . . . . . . .
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UM10360 NXP Semiconductors Chapter 35: Supplementary information 16.14.2 16.14.3 Section configuration registers . . . . . . . . . . . 377 Standard Frame Individual Start Address register (SFF_sa - 0x4003 C004) . . . . . . . . . . . . . . . 378 16.14.4 Standard Frame Group Start Address register (SFF_GRP_sa - 0x4003 C008) . . . . . . . . . . 378 16.14.5 Extended Frame Start Address register (EFF_sa 0x4003 C00C) . . . . . . . . . . . . . . . . . . . . . . . 378 16.14.
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UM10360 NXP Semiconductors Chapter 35: Supplementary information 17.7.7 SPI Interrupt Register (S0SPINT - 0x4002 001C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 17.8 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 Chapter 18: LPC17xx SSP0/1 18.1 18.2 18.3 18.4 18.5 18.5.1 Basic configuration . . . . . . . . . . . . . . . . . . . . 412 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 Description . . . . . . . . . . . . . . . . . . . .
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UM10360 NXP Semiconductors Chapter 35: Supplementary information I2C Monitor mode control register (I2MMCTRL: I2C0, I2C0MMCTRL - 0x4001 C01C; I2C1, I2C1MMCTRL- 0x4005 C01C; I2C2, I2C2MMCTRL- 0x400A 001C) . . . . . . . . . . . 444 19.8.5.1 Interrupt in Monitor mode . . . . . . . . . . . . . . . 445 19.8.5.2 Loss of arbitration in Monitor mode . . . . . . . 445 19.8.
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UM10360 NXP Semiconductors Chapter 35: Supplementary information 20.5 Register description . . . . . . . . . . . . . . . . . . . 20.5.1 Digital Audio Output register (I2SDAO 0x400A 8000) . . . . . . . . . . . . . . . . . . . . . . . . 20.5.2 Digital Audio Input register (I2SDAI 0x400A 8004) . . . . . . . . . . . . . . . . . . . . . . . . 20.5.3 Transmit FIFO register (I2STXFIFO 0x400A 8008) . . . . . . . . . . . . . . . . . . . . . . . . 20.5.4 Receive FIFO register (I2SRXFIFO 0x400A 800C). . . . . . . .
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UM10360 NXP Semiconductors Chapter 35: Supplementary information 23.3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 23.4 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 23.5 Register description . . . . . . . . . . . . . . . . . . . 505 23.5.1 System Timer Control and status register (STCTRL - 0xE000 E010) . . . . . . . . . . . . . . 505 23.5.2 System Timer Reload value register (STRELOAD - 0xE000 E014). . . . . . . . . . . . . . . . . . . . . . . 506 23.5.
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UM10360 NXP Semiconductors Chapter 35: Supplementary information 25.7.6 MCPWM Limit 0-2 registers (MCLIM0-2 0x400B 8024, 0x400B 8028, 0x400B 802C) 533 25.7.6.1 Match and Limit write and operating registers 533 25.7.7 MCPWM Match 0-2 registers (MCMAT0-2 0x400B 8030, 0x400B 8034, 0x400B 8038) . 534 25.7.7.1 Match register in Edge-Aligned mode. . . . . . 534 25.7.7.2 Match register in Center-Aligned mode . . . . 534 25.7.7.3 0 and 100% duty cycle . . . . . . . . . . . . . . . . . 534 25.7.
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UM10360 NXP Semiconductors Chapter 35: Supplementary information Chapter 27: LPC17xx Real-Time Clock (RTC) and backup registers 27.1 Basic configuration . . . . . . . . . . . . . . . . . . . . 558 27.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558 27.3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 558 27.4 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 559 27.5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 560 27.
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UM10360 NXP Semiconductors Chapter 35: Supplementary information 30.3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 30.4 Register description . . . . . . . . . . . . . . . . . . . 30.4.1 D/A Converter Register (DACR - 0x4008 C000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30.4.2 D/A Converter Control register (DACCTRL 0x4008 C004) . . . . . . . . . . . . . . . . . . . . . . . . 582 583 583 30.4.3 30.5 30.5.1 30.5.
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UM10360 NXP Semiconductors Chapter 35: Supplementary information 31.6.2.1 31.6.2.2 31.6.2.3 31.6.3 31.6.3.1 31.6.4 Peripheral-to-memory or memory-to-peripheral DMA flow . . . . . . . . . . . . . . . . . . . . . . . . . . . 609 Peripheral-to-peripheral DMA flow . . . . . . . . 609 Memory-to-memory DMA flow . . . . . . . . . . . 610 Interrupt requests . . . . . . . . . . . . . . . . . . . . . 610 Hardware interrupt sequence flow . . . . . . . . 611 Address generation . . . . . . . . . . . . . . . . . . .
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UM10360 NXP Semiconductors Chapter 35: Supplementary information 33.7 JTAG TAP Identification . . . . . . . . . . . . . . . . 643 Chapter 34: Appendix: Cortex-M3 user guide 34.1 ARM Cortex-M3 User Guide: Introduction. . 644 34.1.1 About the processor and core peripherals . . 644 34.1.1.1 System level interface . . . . . . . . . . . . . . . . . 645 34.1.1.2 Integrated configurable debug . . . . . . . . . . . 645 34.1.1.3 Cortex-M3 processor features and benefits summary . . . . . . . . . . . . . . . . .
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UM10360 NXP Semiconductors Chapter 35: Supplementary information 34.2.5.1.3 Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . 678 Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .679 34.2.5.1.4 Condition flags . . . . . . . . . . . . . . . . . . . . . . . 679 34.2.5.1.5 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 679 34.2.5.1.6 Multiword arithmetic examples . . . . . . . . . . . 679 34.2.5.2 AND, ORR, EOR, BIC, and ORN . . . . . . . . . 681 34.2.5.2.
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UM10360 NXP Semiconductors Chapter 35: Supplementary information 34.2.9.1.3 Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . 34.2.9.1.4 Condition flags . . . . . . . . . . . . . . . . . . . . . . . 34.2.9.1.5 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 34.2.9.2 CBZ and CBNZ. . . . . . . . . . . . . . . . . . . . . . . 34.2.9.2.1 Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34.2.9.2.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 34.
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UM10360 NXP Semiconductors Chapter 35: Supplementary information 34.3.1.6 The Cortex Microcontroller Software Interface Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735 34.3.2 Memory model . . . . . . . . . . . . . . . . . . . . . . . 737 34.3.2.1 Memory regions, types and attributes. . . . . . 737 34.3.2.2 Memory system ordering of memory accesses. . . . . . . . . . . . . . . . . . . . . . . . . . . . 738 34.3.2.3 Behavior of memory accesses . . . . . . . . . . . 739 34.3.2.
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UM10360 NXP Semiconductors Chapter 35: Supplementary information 34.4.5.6 MPU access permission attributes . . . . . . . . 34.4.5.7 MPU mismatch . . . . . . . . . . . . . . . . . . . . . . . 34.4.5.8 Updating an MPU region . . . . . . . . . . . . . . . 34.4.5.8.1 Updating an MPU region using separate words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792 793 793 793 34.4.5.8.2 Updating an MPU region using multi-word writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34.4.