User Manual

UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
User manual Rev. 2 — 19 August 2010 30 of 840
NXP Semiconductors
UM10360
Chapter 4: LPC17xx Clocking and power control
4.2 Register description
All registers, regardless of size, are on word address boundaries. Details of the registers
appear in the description of each function.
Table 14. Summary of system control registers
Name Description Access Reset value Address
Clock source selection
CLKSRCSEL Clock Source Select Register R/W 0 0x400F C10C
Phase Locked Loop (PLL0, Main PLL)
PLL0CON PLL0 Control Register R/W 0 0x400F C080
PLL0CFG PLL0 Configuration Register R/W 0 0x400F C084
PLL0STAT PLL0 Status Register RO 0 0x400F C088
PLL0FEED PLL0 Feed Register WO NA 0x400F C08C
Phase Locked Loop (PLL1, USB PLL)
PLL1CON PLL1 Control Register R/W 0 0x400F C0A0
PLL1CFG PLL1 Configuration Register R/W 0 0x400F C0A4
PLL1STAT PLL1 Status Register RO 0 0x400F C0A8
PLL1FEED PLL1 Feed Register WO NA 0x400F C0AC
Clock dividers
CCLKCFG CPU Clock Configuration Register R/W 0 0x400F C104
USBCLKCFG USB Clock Configuration Register R/W 0 0x400F C108
PCLKSEL0 Peripheral Clock Selection register 0. R/W 0 0x400F C1A8
PCLKSEL1 Peripheral Clock Selection register 1. R/W 0 0x400F C1AC
Power control
PCON Power Control Register R/W 0 0x400F C0C0
PCONP Power Control for Peripherals Register R/W 0x03BE 0x400F C0C4
Utility
CLKOUTCFG Clock Output Configuration Register R/W 0 0x400F C1C8