User Manual

UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
User manual Rev. 2 — 19 August 2010 518 of 840
NXP Semiconductors
UM10360
Chapter 24: LPC17xx Pulse Width Modulator (PWM)
24.6.5 PWM Capture Control Register (PWM1CCR - 0x4001 8028)
The Capture Control Register is used to control whether one of the four Capture Registers
is loaded with the value in the Timer Counter when a capture event occurs, and whether
an interrupt is generated by the capture event. Setting both the rising and falling bits at the
same time is a valid configuration, resulting in a capture event for both edges. In the
descriptions below, “n” represents the Timer number, 0 or 1.
Note: If Counter mode is selected for a particular CAP input in the CTCR, the 3 bits for
that input in this register should be programmed as 000, but capture and/or interrupt can
be selected for the other 3 CAP inputs.
14 PWMMR4S 1 Stop on PWMMR4: the PWMTC and PWMPC will be stopped and PWMTCR[0] will be
set to 0 if PWMMR4 matches the PWMTC.
0
0 This feature is disabled
15 PWMMR5I 1 Interrupt on PWMMR5: An interrupt is generated when PWMMR5 matches the value
in the PWMTC.
0
0 This interrupt is disabled.
16 PWMMR5R 1 Reset on PWMMR5: the PWMTC will be reset if PWMMR5 matches it. 0
0 This feature is disabled.
17 PWMMR5S 1 Stop on PWMMR5: the PWMTC and PWMPC will be stopped and PWMTCR[0] will be
set to 0 if PWMMR5 matches the PWMTC.
0
0 This feature is disabled
18 PWMMR6I 1 Interrupt on PWMMR6: an interrupt is generated when PWMMR6 matches the value in
the PWMTC.
0
0 This interrupt is disabled.
19 PWMMR6R 1 Reset on PWMMR6: the PWMTC will be reset if PWMMR6 matches it. 0
0 This feature is disabled.
20 PWMMR6S 1 Stop on PWMMR6: the PWMTC and PWMPC will be stopped and PWMTCR[0] will be
set to 0 if PWMMR6 matches the PWMTC.
0
31:21 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA
Table 449: Match Control Register (PWM1MCR - address 0x4001 8014) bit description
Bit Symbol Value Description Reset
Value
Table 450: PWM Capture Control Register (PWM1CCR - address 0x4001 8028) bit description
Bit Symbol Value Description Reset
Value
0 Capture on
CAPn.0 rising
edge
0 This feature is disabled. 0
1 A synchronously sampled rising edge on the CAPn.0 input will cause CR0 to be
loaded with the contents of the TC.
1 Capture on
CAPn.0 falling
edge
0 This feature is disabled. 0
1 A synchronously sampled falling edge on CAPn.0 will cause CR0 to be loaded with
the contents of TC.
2 Interrupt on
CAPn.0 event
0 This feature is disabled. 0
1 A CR0 load due to a CAPn.0 event will generate an interrupt.