User Manual

UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
User manual Rev. 2 — 19 August 2010 54 of 840
NXP Semiconductors
UM10360
Chapter 4: LPC17xx Clocking and power control
4.7 Clock dividers
The output of the PLL0 must be divided down for use by the CPU and the USB subsystem
(if used with PLL0, see Section 4.6
). Separate dividers are provided such that the CPU
frequency can be determined independently from the USB subsystem, which always
requires 48 MHz with a 50% duty cycle for proper operation.
4.7.1 CPU Clock Configuration register (CCLKCFG - 0x400F C104)
The CCLKCFG register controls the division of the PLL0 output before it is used by the
CPU. When PLL0 is bypassed, the division may be by 1. When PLL0 is running, the
output must be divided in order to bring the CPU clock frequency (CCLK) within operating
limits. An 8-bit divider allows a range of options, including slowing CPU operation to a low
rate for temporary power savings without turning off PLL0.
Note: when the USB interface is used in an application, CCLK must be at least 18 MHz in
order to support internal operations of the USB subsystem.
Fig 11. PLLs and clock dividers
USB
Clock
Divider
osc_clk
USB PLL settings
(PLL1...)
USB clock divider setting
USBCLKCFG[3:0]
usb_clk
USB PLL
(PLL1)
main PLL
settings
(PLL0...)
USB PLL select
(PLL1CON)
Main PLL
(PLL0)
CPU
Clock
Divider
pllclk
CPU PLL
select
(PLL0CON)
cclk
CPU clock divider setting
CCLKCFG[7:0]
sysclk