User Manual

UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
User manual Rev. 2 — 19 August 2010 562 of 840
NXP Semiconductors
UM10360
Chapter 27: LPC17xx Real-Time Clock (RTC) and backup registers
27.6.1 RTC interrupts
Interrupt generation is controlled through the Interrupt Location Register (ILR), Counter
Increment Interrupt Register (CIIR), the alarm registers, and the Alarm Mask Register
(AMR). Interrupts are generated only by the transition into the interrupt state. The ILR
separately enables CIIR and AMR interrupts. Each bit in CIIR corresponds to one of the
time counters. If CIIR is enabled for a particular counter, then every time the counter is
incremented an interrupt is generated. The alarm registers allow the user to specify a date
and time for an interrupt to be generated. The AMR provides a mechanism to mask alarm
compares. If all non-masked alarm registers match the value in their corresponding time
counter, then an interrupt is generated.
The RTC interrupt can bring the microcontroller out of Power-down mode when the RTC
is operating from its own oscillator on the RTCX1-2 pins. When the RTC interrupt is
enabled for wake-up and its selected event occurs, the oscillator wake-up cycle
associated with the XTAL1/2 pins is started. For details on the RTC based wake-up
process see Section 4.8.8 “
Wake-up from Reduced Power Modes” on page 62 and
Section 4.9 “
Wake-up timer” on page 65.
27.6.2 Miscellaneous register group
27.6.2.1 Interrupt Location Register (ILR - 0x4002 4000)
The Interrupt Location Register is a 2-bit register that specifies which blocks are
generating an interrupt (see Table 508
). Writing a one to the appropriate bit clears the
corresponding interrupt. Writing a zero has no effect. This allows the programmer to read
this register and write back the same value to clear only the interrupt that is detected by
the read.
27.6.2.2 Clock Control Register (CCR - 0x4002 4008)
The clock register is a 4-bit register that controls the operation of the clock divide circuit.
Each bit of the clock register is described in Table 509
. All NC bits in this register should
be initialized when the RTC is first turned on.
Table 508. Interrupt Location Register (ILR - address 0x4002 4000) bit description
Bit Symbol Description Reset
value
0 RTCCIF When one, the Counter Increment Interrupt block generated an interrupt. Writing a one to this bit
location clears the counter increment interrupt.
0
1 RTCALF When one, the alarm registers generated an interrupt. Writing a one to this bit location clears the
alarm interrupt.
0
31:21 - Reserved, user software should not write ones to reserved bits. The value read from a reserved
bit is not defined.
NA
Table 509. Clock Control Register (CCR - address 0x4002 4008) bit description
Bit Symbol Value Description Reset
value
0 CLKEN Clock Enable. NC
1 The time counters are enabled.
0 The time counters are disabled so that they may be initialized.