User Manual

UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
User manual Rev. 2 — 19 August 2010 574 of 840
29.1 Basic configuration
The ADC is configured using the following registers:
1. Power: In the PCONP register (Table 46
), set the PCADC bit.
Remark: On reset, the ADC is disabled. To enable the ADC, first set the PCADC bit,
and then enable the ADC in the AD0CR register (bit PDN Table 531
). To disable the
ADC, first clear the PDN bit, and then clear the PCADC bit.
2. Clock: In the PCLKSEL0 register (Table 40
), select PCLK_ADC. To scale the clock for
the ADC, see bits CLKDIV in Table 531
.
3. Pins: Enable ADC0 pins through PINSEL registers. Select the pin modes for the port
pins with ADC0 functions through the PINMODE registers (Section 8.5
).
4. Interrupts: To enable interrupts in the ADC, see Table 535
. Interrupts are enabled in
the NVIC using the appropriate Interrupt Set Enable register. Disable the ADC
interrupt in the NVIC using the appropriate Interrupt Set Enable register.
5. DMA: See Section 29.6.4
. For GPDMA system connections, see Table 543.
29.2 Features
• 12-bit successive approximation analog to digital converter.
• Input multiplexing among 8 pins.
• Power-down mode.
• Measurement range V
REFN
to V
REFP
(typically 3 V; not to exceed V
DDA
voltage level).
• 12-bit conversion rate of 200 kHz.
• Burst conversion mode for single or multiple inputs.
• Optional conversion on transition on input pin or Timer Match signal.
29.3 Description
Basic clocking for the A/D converters is provided by the APB clock. A programmable
divider is included in each converter to scale this clock to the clock (maximum 13 MHz)
needed by the successive approximation process. A fully accurate conversion requires 65
of these clocks.
UM10360
Chapter 29: LPC17xx Analog-to-Digital Converter (ADC)
Rev. 2 — 19 August 2010 User manual