User Manual

UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
User manual Rev. 2 — 19 August 2010 600 of 840
NXP Semiconductors
UM10360
Chapter 31: LPC17xx General Purpose DMA (GPDMA)
31.5.15 DMA Request Select register (DMAReqSel - 0x400F C1C4)
DMAReqSel is a read/write register that allows selecting between UART or Timer DMA
requests for DMA inputs 8 through 15. Table 559
shows the bit assignments of the
DMAReqSel Register.
31.5.16 DMA Channel registers
The channel registers are used to program the eight DMA channels. These registers
consist of:
• Eight DMACCxSrcAddr Registers.
• Eight DMACCxDestAddr Registers.
• Eight DMACCxLLI Registers.
• Eight DMACCxControl Registers.
• Eight DMACCxConfig Registers.
When performing scatter/gather DMA, the first four of these are automatically updated.
Table 559. DMA Request Select register (DMAReqSel - 0x400F C1C4)
Bit Name Function
0 DMASEL08 Selects the DMA request for GPDMA input 8:
0 - UART0 TX is selected.
1 - Timer 0 match 0 is selected.
1 DMASEL09 Selects the DMA request for GPDMA input 9:
0 - UART0 RX is selected.
1 - Timer 0 match 1 is selected.
2 DMASEL10 Selects the DMA request for GPDMA input 10:
0 - UART1 TX is selected.
1 - Timer 1match 0 is selected.
3 DMASEL11 Selects the DMA request for GPDMA input 11:
0 - UART1 RX is selected.
1 - Timer 1match 1 is selected.
4 DMASEL12 Selects the DMA request for GPDMA input 12:
0 - UART2 TX is selected.
1 - Timer 2 match 0 is selected.
5 DMASEL13 Selects the DMA request for GPDMA input 13:
0 - UART2 RX is selected.
1 - Timer 2 match 1 is selected.
6 DMASEL14 Selects the DMA request for GPDMA input 14:
0 - UART3 TX is selected.
1 - Timer 3 match 0 is selected.
7 DMASEL15 Selects the DMA request for GPDMA input 15:
0 - UART3 RX is selected.
1 - Timer 3 match 1 is selected.
31:8 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.