User Manual

UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
User manual Rev. 2 — 19 August 2010 606 of 840
NXP Semiconductors
UM10360
Chapter 31: LPC17xx General Purpose DMA (GPDMA)
31.5.21.1 Lock control
The lock control may set the lock bit by writing a 1 to bit 16 of the DMACCxConfig
Register. When a burst occurs, the AHB arbiter will not de-grant the master during the
burst until the lock is de-asserted. The DMA Controller can be locked for a a single burst
such as a long source fetch burst or a long destination drain burst. The DMA Controller
does not usually assert the lock continuously for a source fetch burst followed by a
destination drain burst.
There are situations when the DMA Controller asserts the lock for source transfers
followed by destination transfers. This is possible when internal conditions in the DMA
Controller permit it to perform a source fetch followed by a destination drain back-to-back.
31.5.21.2 Transfer type
Table 565 lists the bit values of the transfer type bits identified in Table 564.
Table 565. Transfer type bits
Bit value Transfer type Controller
000 Memory to memory DMA
001 Memory to peripheral DMA
010 Peripheral to memory DMA
011 Source peripheral to destination peripheral DMA
100 to 111 Reserved, do not use these combinations -