User Manual

UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
User manual Rev. 2 — 19 August 2010 762 of 840
NXP Semiconductors
UM10360
Chapter 34: Appendix: Cortex-M3 user guide
34.4.2.4 Interrupt Set-pending Registers
The ISPR0-ISPR3 registers force interrupts into the pending state, and show which
interrupts are pending. See:
• the register summary in Table 644 for the register attributes
• Table 645 for which interrupts are controlled by each register.
The bit assignments are shown in Table 648
.
Remark: Writing 1 to the ISPR bit corresponding to:
• an interrupt that is pending has no effect
• a disabled interrupt sets the state of that interrupt to pending.
34.4.2.5 Interrupt Clear-pending Registers
The ICPR0-ICPR3 registers remove the pending state from interrupts, and show which
interrupts are pending. See:
• the register summary in Table 644 for the register attributes
• Table 645 for which interrupts are controlled by each register.
The bit assignments are shown in Table 649
.
Table 647. ICER bit assignments
Bits Name Function
[31:0] CLRENA Interrupt clear-enable bits.
Write:
0 = no effect
1 = disable interrupt.
Read:
0 = interrupt disabled
1 = interrupt enabled.
Table 648. ISPR bit assignments
Bits Name Function
[31:0] SETPEND Interrupt set-pending bits.
Write:
0 = no effect
1 = changes interrupt state to pending.
Read:
0 = interrupt is not pending
1 = interrupt is pending.