User Manual

UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
User manual Rev. 2 — 19 August 2010 79 of 840
NXP Semiconductors
UM10360
Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC)
6.5.3 Interrupt Clear-Enable Register 0 (ICER0 - 0xE000 E180)
The ICER0 register allows disabling the first 32 peripheral interrupts, or for reading the
enabled state of those interrupts. The remaining interrupts are disabled via the ICER1
register (Section 6.5.4
). Enabling interrupts is done through the ISER0 and ISER1
registers (Section 6.5.1
and Section 6.5.2).
Table 54. Interrupt Clear-Enable Register 0 (ICER0 - 0xE000 E180)
Bit Name Function
0 ICE_WDT Watchdog Timer Interrupt Disable.
Write: writing 0 has no effect, writing 1 disables the interrupt.
Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.
1 ICE_TIMER0 Timer 0 Interrupt Disable. See functional description for bit 0.
2 ICE_TIMER1 Timer 1. Interrupt Disable. See functional description for bit 0.
3 ICE_TIMER2 Timer 2 Interrupt Disable. See functional description for bit 0.
4 ICE_TIMER3 Timer 3 Interrupt Disable. See functional description for bit 0.
5 ICE_UART0 UART0 Interrupt Disable. See functional description for bit 0.
6 ICE_UART1 UART1 Interrupt Disable. See functional description for bit 0.
7 ICE_UART2 UART2 Interrupt Disable. See functional description for bit 0.
8 ICE_UART3 UART3 Interrupt Disable. See functional description for bit 0.
9 ICE_PWM PWM1 Interrupt Disable. See functional description for bit 0.
10 ICE_I2C0 I
2
C0 Interrupt Disable. See functional description for bit 0.
11 ICE_I2C1 I
2
C1 Interrupt Disable. See functional description for bit 0.
12 ICE_I2C2 I
2
C2 Interrupt Disable. See functional description for bit 0.
13 ICE_SPI SPI Interrupt Disable. See functional description for bit 0.
14 ICE_SSP0 SSP0 Interrupt Disable. See functional description for bit 0.
15 ICE_SSP1 SSP1 Interrupt Disable. See functional description for bit 0.
16 ICE_PLL0 PLL0 (Main PLL) Interrupt Disable. See functional description for bit 0.
17 ICE_RTC Real Time Clock (RTC) Interrupt Disable. See functional description for bit 0.
18 ICE_EINT0 External Interrupt 0 Interrupt Disable. See functional description for bit 0.
19 ICE_EINT1 External Interrupt 1 Interrupt Disable. See functional description for bit 0.
20 ICE_EINT2 External Interrupt 2 Interrupt Disable. See functional description for bit 0.
21 ICE_EINT3 External Interrupt 3 Interrupt Disable. See functional description for bit 0.
22 ICE_ADC ADC Interrupt Disable. See functional description for bit 0.
23 ICE_BOD BOD Interrupt Disable. See functional description for bit 0.
24 ICE_USB USB Interrupt Disable. See functional description for bit 0.
25 ICE_CAN CAN Interrupt Disable. See functional description for bit 0.
26 ICE_DMA GPDMA Interrupt Disable. See functional description for bit 0.
27 ICE_I2S I
2
S Interrupt Disable. See functional description for bit 0.
28 ICE_ENET Ethernet Interrupt Disable. See functional description for bit 0.
29 ICE_RIT Repetitive Interrupt Timer Interrupt Disable. See functional description for bit 0.
30 ICE_MCPWM Motor Control PWM Interrupt Disable. See functional description for bit 0.
31 ICE_QEI Quadrature Encoder Interface Interrupt Disable. See functional description for bit 0.