User Manual

ManualsBrandsPololu ManualsARM ControllersARM mbed NXP LPC1768 Development Board

811

812

813

814

815

816

817

818

819

820

User manual Rev. 2 — 19 August 2010 813 of 840

NXP Semiconductors

UM10360

Chapter 35: Supplementary information

Table 566. DMA request signal usage . . . . . . . . . . . . . .609

Table 567. Sectors in a LPC17xx device. . . . . . . . . . . . .620

Table 568. Code Read Protection options

[1]

. . . . . . . . . .621

Table 569. Code Read Protection hardware/software

interaction. . . . . . . . . . . . . . . . . . . . . . . . . . . .622

Table 570. ISP command summary. . . . . . . . . . . . . . . . .623

Table 571. ISP Unlock command . . . . . . . . . . . . . . . . . .623

Table 572. ISP Set Baud Rate command . . . . . . . . . . . .624

Table 573. Correlation between possible ISP baudrates and

CCLK frequency (in MHz). . . . . . . . . . . . . . . .624

Table 574. ISP Echo command. . . . . . . . . . . . . . . . . . . .624

Table 575. ISP Write to RAM command . . . . . . . . . . . . .625

Table 576. ISP Read Memory command. . . . . . . . . . . . .625

Table 577. ISP Prepare sector(s) for write operation

command . . . . . . . . . . . . . . . . . . . . . . . . . . . .626

Table 578. ISP Copy command. . . . . . . . . . . . . . . . . . . .626

Table 579. ISP Go command. . . . . . . . . . . . . . . . . . . . . .627

Table 580. ISP Erase sector command. . . . . . . . . . . . . .627

Table 581. ISP Blank check sector command . . . . . . . . .628

Table 582. ISP Read Part Identification command . . . . .628

Table 583. LPC17xx part identification numbers . . . . . . .628

Table 584. ISP Read Boot Code version number command.

629

Table 585. ISP Read device serial number command. . .629

Table 586. ISP Compare command. . . . . . . . . . . . . . . . .629

Table 587. ISP Return Codes Summary . . . . . . . . . . . . .630

Table 588. IAP Command Summary. . . . . . . . . . . . . . . .632

Table 589. IAP Prepare sector(s) for write operation

command . . . . . . . . . . . . . . . . . . . . . . . . . . . .633

Table 590. IAP Copy RAM to Flash command . . . . . . . .633

Table 591. IAP Erase Sector(s) command . . . . . . . . . . .634

Table 592. IAP Blank check sector(s) command. . . . . . .634

Table 593. IAP Read part identification number command . .

634

Table 594. IAP Read Boot Code version number command.

635

Table 595. IAP Read device serial number command. . .635

Table 596. IAP Compare command. . . . . . . . . . . . . . . . .635

Table 597. Re-invoke ISP . . . . . . . . . . . . . . . . . . . . . . . .636

Table 598. IAP Status Codes Summary . . . . . . . . . . . . .636

Table 599. Register overview: FMC (base address 0x4008

4000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .637

Table 600. Flash Module Signature Start register

(FMSSTART - 0x4008 4020) bit description. .638

Table 601. Flash Module Signature Stop register (FMSSTOP

- 0x4008 4024) bit description . . . . . . . . . . . .638

Table 602. FMSW0 register bit description (FMSW0,

address: 0x4008 402C) . . . . . . . . . . . . . . . . .638

Table 603. FMSW1 register bit description (FMSW1,

address: 0x4008 4030) . . . . . . . . . . . . . . . . .638

Table 604. FMSW2 register bit description (FMSW2,

address: 0x4008 4034) . . . . . . . . . . . . . . . . .639

Table 605. FMSW3 register bit description (FMSW3,

address: 0x4008 4038) . . . . . . . . . . . . . . . . .639

Table 606. Flash module Status register (FMSTAT - 0x4008

4FE0) bit description. . . . . . . . . . . . . . . . . . . .639

Table 607. Flash Module Status Clear register (FMSTATCLR

- 0x0x4008 4FE8) bit description . . . . . . . . . .639

Table 608. JTAG pin description. . . . . . . . . . . . . . . . . . . 642

Table 609. Serial Wire Debug pin description. . . . . . . . . 642

Table 610. Parallel Trace pin description . . . . . . . . . . . . 642

Table 611. Memory Mapping Control register (MEMMAP -

0x400F C040) bit description . . . . . . . . . . . . . 643

Table 612. Cortex-M3 instructions . . . . . . . . . . . . . . . . 647

Table 613. CMSIS intrinsic functions to generate some

Cortex-M3 instructions. . . . . . . . . . . . . . . . . . 650

Table 614. CMSIS intrinsic functions to access the special

registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650

Table 615. Condition code suffixes . . . . . . . . . . . . . . . . . 657

Table 616. Memory access instructions . . . . . . . . . . . . . 660

Table 617. Offset ranges. . . . . . . . . . . . . . . . . . . . . . . . . 663

Table 618. Offset ranges. . . . . . . . . . . . . . . . . . . . . . . . . 669

Table 619. Data processing instructions. . . . . . . . . . . . . 677

Table 620. Multiply and divide instructions . . . . . . . . . . . 692

Table 621. Packing and unpacking instructions . . . . . . . 700

Table 622. Branch and control instructions. . . . . . . . . . . 705

Table 623. Branch ranges. . . . . . . . . . . . . . . . . . . . . . . . 706

Table 624. Miscellaneous instructions . . . . . . . . . . . . . . 714

Table 625. Summary of processor mode, execution privilege

level, and stack use options. . . . . . . . . . . . . . 728

Table 626. Core register set summary . . . . . . . . . . . . . . 728

Table 627. PSR register combinations . . . . . . . . . . . . . . 730

Table 628. APSR bit assignments . . . . . . . . . . . . . . . . . 731

Table 629. IPSR bit assignments . . . . . . . . . . . . . . . . . . 732

Table 630. EPSR bit assignments . . . . . . . . . . . . . . . . . 732

Table 631. PRIMASK register bit assignments . . . . . . . . 733

Table 632. FAULTMASK register bit assignments . . . . . 733

Table 633. BASEPRI register bit assignments . . . . . . . . 734

Table 634. CONTROL register bit assignments . . . . . . . 734

Table 635. Memory access behavior . . . . . . . . . . . . . . . 739

Table 636. SRAM memory bit-banding regions . . . . . . . 741

Table 637. Peripheral memory bit-banding regions . . . . 741

Table 638. C compiler intrinsic functions for exclusive access

instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . 744

Table 639. Properties of the different exception types . . 746

Table 640. Exception return behavior . . . . . . . . . . . . . . . 751

Table 641. Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753

Table 642. Fault status and fault address registers . . . . 754

Table 643. Core peripheral register regions . . . . . . . . . . 759

Table 644. NVIC register summary. . . . . . . . . . . . . . . . . 760

Table 645. Mapping of interrupts to the interrupt variables. .

761

Table 646. ISER bit assignments . . . . . . . . . . . . . . . . . . 761

Table 647. ICER bit assignments . . . . . . . . . . . . . . . . . . 762

Table 648. ISPR bit assignments . . . . . . . . . . . . . . . . . . 762

Table 649. ICPR bit assignments . . . . . . . . . . . . . . . . . . 763

Table 650. IABR bit assignments . . . . . . . . . . . . . . . . . . 763

Table 651. IPR bit assignments . . . . . . . . . . . . . . . . . . . 764

Table 652. STIR bit assignments . . . . . . . . . . . . . . . . . . 764

Table 653. CMSIS functions for NVIC control. . . . . . . . . 766

Table 654. Summary of the system control block registers .

767

Table 655. ACTLR bit assignments . . . . . . . . . . . . . . . . 768

Table 656. CPUID register bit assignments . . . . . . . . . . 768

Table 657. ICSR bit assignments . . . . . . . . . . . . . . . . . . 769

Table 658. VTOR bit assignments . . . . . . . . . . . . . . . . . 771