User Manual

UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
User manual Rev. 2 — 19 August 2010 835 of 840
continued >>
NXP Semiconductors
UM10360
Chapter 35: Supplementary information
31.6.2.1 Peripheral-to-memory or memory-to-peripheral
DMA flow . . . . . . . . . . . . . . . . . . . . . . . . . . . 609
31.6.2.2 Peripheral-to-peripheral DMA flow . . . . . . . . 609
31.6.2.3 Memory-to-memory DMA flow . . . . . . . . . . . 610
31.6.3 Interrupt requests . . . . . . . . . . . . . . . . . . . . . 610
31.6.3.1 Hardware interrupt sequence flow . . . . . . . . 611
31.6.4 Address generation . . . . . . . . . . . . . . . . . . . 611
31.6.4.1 Word-aligned transfers across a boundary . . 611
31.6.5 Scatter/gather . . . . . . . . . . . . . . . . . . . . . . . . 611
31.6.5.1 Linked list items . . . . . . . . . . . . . . . . . . . . . . 612
31.6.5.1.1 Programming the DMA controller for
scatter/gather DMA . . . . . . . . . . . . . . . . . . . 612
31.6.5.1.2 Example of scatter/gather DMA. . . . . . . . . . 612
Chapter 32: LPC17xx Flash memory interface and programming
32.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 615
32.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615
32.3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 615
32.3.1 Memory map after any reset. . . . . . . . . . . . . 616
32.3.1.1 Criterion for Valid User Code . . . . . . . . . . . . 616
32.3.2 Communication protocol. . . . . . . . . . . . . . . . 617
32.3.2.1 ISP command format . . . . . . . . . . . . . . . . . . 617
32.3.2.2 ISP response format. . . . . . . . . . . . . . . . . . . 617
32.3.2.3 ISP data format. . . . . . . . . . . . . . . . . . . . . . . 617
32.3.2.4 ISP flow control. . . . . . . . . . . . . . . . . . . . . . . 618
32.3.2.5 ISP command abort . . . . . . . . . . . . . . . . . . . 618
32.3.2.6 Interrupts during IAP. . . . . . . . . . . . . . . . . . . 618
32.3.2.7 RAM used by ISP command handler . . . . . . 618
32.3.2.8 RAM used by IAP command handler . . . . . . 618
32.4 Boot process flowchart. . . . . . . . . . . . . . . . . 619
32.5 Sector numbers . . . . . . . . . . . . . . . . . . . . . . . 620
32.6 Code Read Protection (CRP) . . . . . . . . . . . . 621
32.7 ISP commands . . . . . . . . . . . . . . . . . . . . . . . . 623
32.7.1 Unlock <Unlock code> . . . . . . . . . . . . . . . . . 623
32.7.2 Set Baud Rate <Baud Rate> <stop bit> . . . . 624
32.7.3 Echo <setting> . . . . . . . . . . . . . . . . . . . . . . . 624
32.7.4 Write to RAM <start address> <number of
bytes>. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624
32.7.5 Read Memory <address> <no. of bytes> . . . 625
32.7.6 Prepare sector(s) for write operation <start sector
number> <end sector number> . . . . . . . . . . 626
32.7.7 Copy RAM to Flash <flash address> <RAM
address> <no of bytes> . . . . . . . . . . . . . . . . 626
32.7.8 Go <address> <mode>. . . . . . . . . . . . . . . . . 627
32.7.9 Erase sector(s) <start sector number> <end
sector number>. . . . . . . . . . . . . . . . . . . . . . . 627
32.7.10 Blank check sector(s) <sector number> <end
sector number>. . . . . . . . . . . . . . . . . . . . . . . 628
32.7.11 Read Part Identification number . . . . . . . . . 628
32.7.12 Read Boot Code version number. . . . . . . . . 629
32.7.13 Read device serial number . . . . . . . . . . . . . 629
32.7.14 Compare <address1> <address2> <no of
bytes> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629
32.7.15 ISP Return Codes . . . . . . . . . . . . . . . . . . . . 630
32.8 IAP commands . . . . . . . . . . . . . . . . . . . . . . . 631
32.8.1 Prepare sector(s) for write operation . . . . . . 632
32.8.2 Copy RAM to Flash . . . . . . . . . . . . . . . . . . . 633
32.8.3 Erase Sector(s) . . . . . . . . . . . . . . . . . . . . . . 634
32.8.4 Blank check sector(s). . . . . . . . . . . . . . . . . . 634
32.8.5 Read part identification number . . . . . . . . . . 634
32.8.6 Read Boot Code version number. . . . . . . . . 635
32.8.7 Read device serial number . . . . . . . . . . . . . 635
32.8.8 Compare <address1> <address2> <no of
bytes> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
32.8.9 Re-invoke ISP . . . . . . . . . . . . . . . . . . . . . . . 636
32.8.10 IAP Status Codes. . . . . . . . . . . . . . . . . . . . . 636
32.9 JTAG flash programming interface . . . . . . . 636
32.10 Flash signature generation . . . . . . . . . . . . . 637
32.10.1 Register description for signature generation 637
32.10.1.1 Signature generation address and control
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638
32.10.1.2 Signature generation result registers . . . . . . 638
32.10.1.3 Flash Module Status register (FMSTAT -
0x0x4008 4FE0). . . . . . . . . . . . . . . . . . . . . . 639
32.10.1.4 Flash Module Status Clear register (FMSTATCLR
- 0x0x4008 4FE8) . . . . . . . . . . . . . . . . . . . . 639
32.10.2 Algorithm and procedure for signature
generation . . . . . . . . . . . . . . . . . . . . . . . . . . 640
Signature generation . . . . . . . . . . . . . . . . . . . 640
Content verification . . . . . . . . . . . . . . . . . . . . 640
Chapter 33: LPC17xx JTAG, Serial Wire Debug (SWD), and Trace
33.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641
33.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 641
33.3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 641
33.4 Pin Description . . . . . . . . . . . . . . . . . . . . . . . 641
33.5 Debug Notes . . . . . . . . . . . . . . . . . . . . . . . . . 642
33.6 Debug memory re-mapping . . . . . . . . . . . . . 643
33.6.1 Memory Mapping Control register (MEMMAP -
0x400F C040) . . . . . . . . . . . . . . . . . . . . . . . 643