Data Sheet

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Wide V

1A Synchronous Buck Regulator

ISL85410

The ISL85410 is a 1A synchronous buck regulator with an

input range of 3V to 36V. It provides an easy to use, high

efficiency low BOM count solution for a variety of applications.

The ISL85410 integrates both high-side and low-side NMOS

FETs and features a PFM mode for improved efficiency at light

loads. This feature can be disabled if a forced PWM mode is

desired. The part switches at a default frequency of 500kHz

but may also be programmed using an external resistor from

300kHz to 2MHz. The ISL85410 has the ability to utilize

internal or external compensation. By integrating both NMOS

devices and providing internal configuration options, minimal

external components are required, reducing BOM count and

complexity of design.

With the wide V

range and reduced BOM, the part provides

an easy to implement design solution for a variety of

applications while giving superior performance. It will provide

a very robust design for high voltage industrial applications as

well as an efficient solution for battery powered applications.

The part is available in a small Pb-free 4mmx3mm DFN plastic

package with a full-range industrial temperature of -40°C to

+125°C.

Related Literature

• AN1905, “ISL85410EVAL1Z, ISL85418EVAL1Z Wide V

1A,

800mA Synchronous Buck Regulator”

• AN1908

, “ISL85410DEMO1Z, ISL85418DEMO1Z Wide V

1A, 800mA Synchronous Buck Regulator”

Features

• Wide input voltage range 3V to 36V

• Synchronous operation for high efficiency

• No compensation required

• Integrated high-side and low-side NMOS devices

• Selectable PFM or forced PWM mode at light loads

• Internal fixed (500kHz) or adjustable switching frequency

300kHz to 2MHz

• Continuous output current up to 1A

• Internal or external soft-start

• Minimal external components required

• Power-good and enable functions available

Applications

• Industrial control

•Medical devices

•Portable instrumentation

• Distributed power supplies

• Cloud infrastructure

FIGURE 1. TYPICAL APPLICATION FIGURE 2. EFFICIENCY vs LOAD, PFM, V

OUT

= 3.3V

GND

BOOT

100nF

PHASE

SYNC

BOOT

VIN

PGND

COMP

VCC

1µF

VIN

10µF

22µH

INTERNAL DEFAULT PARAMETER SELECTION

OUT

10µF

OUT

100

= 5V

= 15V

= 24V

= 12V

= 33V

OUTPUT LOAD (A)

EFFICIENCY (%)

0 0.10.20.30.40.50.60.70.80.91.0

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

July 24, 2014

FN8375.5

Summary of content (21 pages)

PAGE 1
Wide VIN 1A Synchronous Buck Regulator ISL85410 Features The ISL85410 is a 1A synchronous buck regulator with an input range of 3V to 36V. It provides an easy to use, high efficiency low BOM count solution for a variety of applications. • Wide input voltage range 3V to 36V • Synchronous operation for high efficiency • No compensation required The ISL85410 integrates both high-side and low-side NMOS FETs and features a PFM mode for improved efficiency at light loads.
PAGE 2
ISL85410 Table of Contents Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Typical Application Schematics. . . . . . . . . . . . . . . . . . . . . . . .
PAGE 3
ISL85410 Pin Configuration ISL85410 (12 LD 3x4 DFN) TOP VIEW 12 FS SS 1 11 COMP SYNC 2 10 FB BOOT 3 VIN 4 GND 9 VCC PHASE 5 8 PG PGND 6 7 EN Pin Descriptions PIN NUMBER SYMBOL 1 SS The SS pin controls the soft-start ramp time of the output. A single capacitor from the SS pin to ground determines the output ramp rate. See “Soft-Start” on page 14 for soft-start details. If the SS pin is tied to VCC, an internal soft-start of 2ms will be used.
PAGE 4
ISL85410 Typical Application Schematics 1 2 3 CBOOT 100nF 4 CVIN 10µF VOUT 5 L1 22µH COUT 10µF 6 SS FS COMP SYNC 12 11 R2 CFB 10 BOOT FB GND 9 VIN R3 VCC PHASE CVCC 1µF PG PGND EN FIGURE 3. INTERNAL DEFAULT PARAMETER SELECTION 1 CSS SS FS 2 COMP SYNC 3 CBOOT 100nF 4 CVIN 10µF 5 VOUT COUT 10µF L1 22µH 6 12 RFS 11 R2 CFB 10 BOOT FB GND 9 VIN R3 VCC PHASE CVCC 1µF PG PGND RCOMP EN CCOMP FIGURE 4. USER PROGRAMMABLE PARAMETER SELECTION TABLE 1.
PAGE 5
ISL85410 FB POWERGOOD LOGIC EN/SOFTSTART FB 5M VCC BIAS LDO 500mV/A CURRENT SENSE GATE DRIVE AND PWM DEADTIME OSCILLATOR SYNC PWM/PFM SELECT LOGIC PFM CURRENT SET 5M BOOT FAULT LOGIC 600mV VREF FS VIN PG EN SS Functional Block Diagram FB PWM s Q R Q ZERO CURRENT DETECTION PHASE PGND 450mV/T SLOPE COMPENSATION (PWM ONLY) gm 150k PACKAGE PADDLE COMP GND INTERNAL 54pF COMPENSATION INTERNAl = 50µA/V EXTERNAL = 230µA/V Ordering Information PART NUMBER (Notes 1, 2, 3) PART MARKING
PAGE 6
ISL85410 Absolute Maximum Ratings Thermal Information VIN to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +42V PHASE to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN+0.3V (DC) PHASE to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2V to 43V (20ns) EN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +42V BOOT to PHASE . . . . . . . . . . . . . . . . .
PAGE 7
ISL85410 Electrical Specifications TA = -40°C to +125°C, VIN = 3V to 36V, unless otherwise noted. Typical values are at TA = +25°C. Boldface limits apply across the junction temperature range, -40°C to +125°C (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN (Note 8) TYP MAX (Note 8) 90 94 UNITS POWER-GOOD Lower PG Threshold - VFB Rising Lower PG Threshold - VFB Falling 82.5 Upper PG Threshold - VFB Rising 86 116.
PAGE 8
ISL85410 Efficiency Curves fSW = 500kHz, TA = +25°C 100 100 95 95 90 VIN = 24V 85 VIN = 15V EFFICIENCY (%) EFFICIENCY (%) 90 80 VIN = 33V 75 70 65 75 70 55 55 0.1 0.2 0.3 0.4 0.5 0.6 0.7 OUTPUT LOAD (A) 0.8 0.9 50 1.0 VIN = 33V 65 60 0 0 FIGURE 5. EFFICIENCY vs LOAD, PFM, VOUT = 12V 100 90 85 85 VIN = 15V VIN = 24V 75 70 65 0.3 0.4 0.5 0.6 0.7 0.8 0.9 50 1.0 VIN = 15V 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 OUTPUT LOAD (A) FIGURE 8.
PAGE 9
ISL85410 Efficiency Curves fSW = 500kHz, TA = +25°C (Continued) 100 100 95 VIN = 5V 90 85 EFFICIENCY (%) EFFICIENCY (%) 90 80 VIN = 15V 75 70 VIN = 33V 65 VIN = 24V 60 VIN = 12V 95 VIN = 12V VIN = 5V 85 80 75 70 VIN = 15V 65 60 VIN = 24V 55 55 50 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 50 1.0 0 0.1 0.2 0.3 5.004 0.6 0.7 0.8 0.9 1.0 5.030 5.003 5.025 VIN = 6V VIN = 12V 5.001 OUTPUT VOLTAGE (V) 5.002 OUTPUT VOLTAGE (V) 0.5 FIGURE 12.
PAGE 10
ISL85410 Efficiency Curves 1.810 1.816 OUTPUT VOLTAGE (V) VIN = 12V 1.808 OUTPUT VOLTAGE (V) 1.818 VIN = 5V VIN = 15V 1.809 fSW = 500kHz, TA = +25°C (Continued) 1.807 1.806 1.805 1.804 VIN = 33V 1.803 VIN = 24V 1.802 1.812 VIN = 12V 1.810 VIN = 15V 1.808 1.806 1.804 VIN = 33V 1.802 1.801 1.800 VIN = 5V 1.814 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 OUTPUT LOAD (A) 0.8 0.9 FIGURE 17. VOUT REGULATION vs LOAD, PWM, VOUT = 1.8V Measurements 1.0 1.800 0 0.1 0.2 0.3 VIN = 24V 0.4 0.
PAGE 11
ISL85410 Measurements fSW = 500kHz, VIN = 24V, VOUT = 3.3V, TA = +25°C (Continued) LX 20V/DIV LX 20V/DIV VOUT 2V/DIV VOUT 2V/DIV IL 500mA/DIV IL 500mA/DIV PG 2V/DIV PG 2V/DIV 5ms/DIV 200µs/DIV FIGURE 23. START-UP AT 1A, PWM FIGURE 24. SHUTDOWN AT 1A, PWM LX 20V/DIV LX 20V/DIV VOUT 2V/DIV VOUT 2V/DIV IL 500mA/DIV IL 500mA/DIV PG 2V/DIV PG 2V/DIV 5ms/DIV 200µs/DIV FIGURE 25. START-UP AT 1A, PFM FIGURE 26. SHUTDOWN AT 1A, PFM LX 5V/DIV LX 5V/DIV 5ns/DIV 5ns/DIV FIGURE 27.
PAGE 12
ISL85410 Measurements fSW = 500kHz, VIN = 24V, VOUT = 3.3V, TA = +25°C (Continued) LX 20V/DIV LX 20V/DIV VOUT 20mV/DIV VOUT 20mV/DIV IL 20mA/DIV IL 20mA/DIV 10ms/DIV 1µs/DIV FIGURE 29. STEADY STATE AT NO LOAD, PFM FIGURE 30. STEADY STATE AT NO LOAD, PWM LX 20V/DIV LX 20V/DIV VOUT 20mV/DIV VOUT 50mV/DIV IL 1A/DIV IL 200mA/DIV 1µs/DIV 10µs/DIV FIGURE 31. STEADY STATE AT 1A, PWM FIGURE 32.
PAGE 13
ISL85410 Measurements fSW = 500kHz, VIN = 24V, VOUT = 3.3V, TA = +25°C (Continued) LX 20V/DIV VOUT 100mV/DIV VOUT 20mV/DIV IL 1A/DIV IL 1A/DIV 200µs/DIV 10µs/DIV FIGURE 35. LOAD TRANSIENT, PWM FIGURE 36. PFM TO PWM TRANSITION LX 20V/DIV LX 20V/DIV VOUT 2V/DIV VOUT 2V/DIV IL 1A/DIV IL 1A/DIV PG 2V/DIV PG 2V/DIV 10ms/DIV 50µs/DIV FIGURE 37. OVERCURRENT PROTECTION, PWM FIGURE 38.
PAGE 14
ISL85410 Measurements fSW = 500kHz, VIN = 24V, VOUT = 3.3V, TA = +25°C (Continued) LX 20V/DIV VOUT 5V/DIV VOUT 2V/DIV IL 500mA/DIV PG 2V/DIV PG 2V/DIV 200µs/DIV 500µs/DIV FIGURE 42. OVER-TEMPERATURE PROTECTION, PWM FIGURE 41. NEGATIVE CURRENT LIMIT RECOVERY, PWM Detailed Description Power-Good The ISL85410 combines a synchronous buck PWM controller with integrated power switches. The buck controller drives internal high-side and low-side N-channel MOSFETs to deliver load current up to 1A.
PAGE 15
ISL85410 PWM DCM PULSE SKIP PWM DCM CLOCK 8 CYCLES IL LOAD CURRENT 0 VOUT FIGURE 43. DCM MODE OPERATION WAVEFORMS Output Voltage Selection VCOMP The regulator output voltage is easily programmed using an external resistor divider to scale VOUT relative to the internal reference voltage. The scaled voltage is applied to the inverting input of the error amplifier; refer to Figure 45.
PAGE 16
ISL85410 Should the output fault persist, the regulator will repeat the hiccup sequence indefinitely. There is no danger even if the output is shorted during soft-start. If VOUT is shorted very quickly, FB may collapse below 5/8ths of its target value before 17 cycles of overcurrent are detected. The ISL85410 recognizes this condition and will begin to lower its switching frequency proportional to the FB pin voltage.
PAGE 17
ISL85410 Buck Regulator Output Capacitor Selection ^ Vin + ILd^ 1:D RLP vo^ Vind^ Rc Co Ro Ti(S) d^ K Fm + Tv(S) He(S) ^ V comp -Av(S) FIGURE 47. SMALL SIGNAL MODEL OF SYNCHRONOUS BUCK REGULATOR Vo R2 C3 VFB VREF The following equations allow calculation of the required capacitance to meet a desired ripple voltage level. Additional capacitance may be used.
PAGE 18
ISL85410 2f c V o C o R t 3 R 6 = ---------------------------------- = 22.75 10  f c V o C o GM  V FB 60 (EQ. 9) 45 Where GM is the transconductance, gm, of the voltage error amplifier in each phase. Compensator capacitor C6 is then given by Equation 10. (EQ.
PAGE 19
ISL85410 Layout Considerations The boot capacitor is easily placed on the PCB side opposite the controller IC and 2 vias directly connect the capacitor to BOOT and PHASE. Place the feedback divider close to the FB pin and do not route any feedback components near PHASE or BOOT. If external components are used for SS, COMP or FS the same advice applies. CSS CSS RFS RFS CVIN CVIN 0.50” A multi-layer printed circuit board with GND plane is recommended.
PAGE 20
ISL85410 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE REVISION CHANGE July 24, 2014 FN8375.5 Changed title of Figure 13, on page 9 from “Efficiency vs Load, PWM, VOUT = 5V, L1 = 30µH” to “VOUT Regulation vs Load, PWM, VOUT = 5V, L1 = 30µH”. Replaced Figure Figure 46, on page 16. Updated POD from L12.4x3 to L12.3x4 February 25, 2014 FN8375.
PAGE 21
ISL85410 Package Outline Drawing L12.3x4 12 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 12/11 3.00 B 6 PIN 1 INDEX AREA 1 12 4.00 (4X) 6 PIN #1 INDEX AREA SEE DETAIL "X" A 3.30 ±0.10 0.10 2X 2.50 6 7 12X 0.25 ±0.05 0.10 M C A B TOP VIEW 0.90 MAX 1.70 ±0.10 4 C SIDE VIEW 10X 0.50 12X 0.40 ± 0.05 BOTTOM VIEW (12X 0.60) ( 12 X 0.25) ( 3.30 ) ( 2.50) 0.10 C (10x 0.50) C 0 . 203 REF SEATING PLANE (1.70) 0.08 C 0 . 00 MIN. 0 . 05 MAX. ( 2.