Data Sheet

User manual Rev. 6 — 4 April 2014 20 of 64

NXP Semiconductors

UM10204

C-bus specification and user manual

After the START condition S has been transmitted by a master which requires bus access,

the START byte (0000 0001) is transmitted. Another microcontroller can therefore sample

the SDA line at a low sampling rate until one of the seven zeros in the START byte is

detected. After detection of this LOW level on the SDA line, the microcontroller can switch

to a higher sampling rate to find the repeated START condition Sr which is then used for

synchronization.

A hardware receiver resets upon receipt of the repeated START condition Sr and

therefore ignores the START byte.

An acknowledge-related clock pulse is generated after the START byte. This is present

only to conform with the byte handling format used on the bus. No device is allowed to

acknowledge the START byte.

3.1.16 Bus clear

In the unlikely event where the clock (SCL) is stuck LOW, the preferential procedure is to

reset the bus using the HW reset signal if your I

C devices have HW reset inputs. If the

C devices do not have HW reset inputs, cycle power to the devices to activate the

mandatory internal Power-On Reset (POR) circuit.

If the data line (SDA) is stuck LOW, the master should send nine clock pulses. The device

that held the bus LOW should release it sometime within those nine clocks. If not, then

use the HW reset or cycle power to clear the bus.

3.1.17 Device ID

The Device ID field (see Figure 20) is an optional 3-byte read-only (24 bits) word giving

the following information:

• Twelve bits with the manufacturer name, unique per manufacturer (for example, NXP)

• Nine bits with the part identification, assigned by manufacturer (for example,

PCA9698)

• Three bits with the die revision, assigned by manufacturer (for example, RevX)

Fig 19. START byte procedure

002aac997

9821

NACK

dummy

acknowledge

(HIGH)

START byte 0000 0001

SDA

SCL