Specifications

Prism Media Products Limited AD-2 Dual-rate A/D converter
Operation Manual
Issue 0.2 © Prism Media Products Limited
11 August 1998 Page 45 of 58
implementations of this interface do not use the synchronization pattern to identify the sample word boundary.
Such equipment will often require delays to be carefully matched before it will work correctly. The AD-2 Dual-
rate A/D converter uses a rugged algorithm to correctly decode SDIF data independent of delays or phase.
7.4.6. Coaxial wordclock (WCK) input
This input can be used to lock the AD-2 Dual-rate A/D converter to a sample rate
square wave, or word-clock.
Input impedance: 75S
Input level: 200mV to 10V pk-pk
Mark-space ratio: 40:60 to 60:40
Sync reference point: Rising edge
This input is ac coupled so that in addition to operation with the TTL levels of SDIF-2
word clock sources it will also work with lower signal levels, such as from a double or
triple terminated source, with an optimum noise margin.
Note: When using WCK synchronization the digital outputs of the AD-2 Dual-rate A/D converter are timed so
that the start of the sample frame is coincident with the timing reference point (the rising edge of WCK).
Specified delay measurements are also made from the timing reference point. This input is not required if
the AD-2 Dual-rate A/D converter is configured as clock master.
7.4.7. BNC inputs operating in DSD mode
When the coaxial inputs are set to DSD mode they receive a heavily oversampled
pulse density modulated input signal on the two coaxial data inputs, one for each
channel. The data is TTL-level as described in the section above.
7.4.8. Coaxial clock input operating as DSD input clock
When the coaxial inputs are set to DSD mode, the normal wordclock input format
changes to a DSD bit-clock. Data is clocked into the AD-2 on the rising edge of the
clock. The clock is TTL-level as described in the section above.
Note: DSD operation of the BNC inputs requires an upgrade option.
7.4.9. General behaviour with IEC958/AES3 format inputs
Jitter Tolerance
Above 12kHz: 0.5UI (88.6ns at fs = 44.1kHz)
50Hz to 12kHz: Increases with falling jitter frequency.
e.g. 0.75UI at 8kHz
30UI at 200Hz
Below 50Hz: > 128UI (22.7us at fs=44.1kHz)