Manual

1.21
Operation Manual
© 2016 Prism Media Products Ltd
Revision 1.01Prism Sound Callia
latency. That feature is not available or necessary for use with Callia.
Callia should be able to play audio files and streams reliably even at high bit rates (such as DSD128
or 384kHz 32 bit PCM) simply by ensuring that adequate buffering is chosen within the player
application. However, there is a possibility - particularly in older or badly-configured Windows
systems - that glitches or interruptions may occur in playback of higher bit rates despite long player
buffers, as a consequence of a problem known as 'DPC latency'. This is a result of driver contentions
which can cause the low level audio shovelling to be inadequately serviced. There many discussions
of how to diagnose and cure this problem on the web, including a troubleshooting guide among the
Tech Notes in the support section at www.prismsound.com/optimizePCaudio.
6.2 Clocking and jitter
Good clock stability is probably the single most important issue separating good-quality audio
converters from the rest. With the linearity of modern A/D and D/A converter chips beginning to rival
and exceed the performance of the best analogue circuits, digital recordings would already be
beyond reproach if clock stability did not so often degrade their potential quality.
Why is good clock stability so rare? Probably because most conversion equipment has to
compromise between clock stability, operational requirements and cost. The ideal clock system in an
A/D or D/A converter would be ultimately stable, i.e. would exhibit no jitter (frequency variations) at the
point of conversion, whether operating from an internal clock or from an external synchronization
reference of any format and at any sample rate. But this is a very tall order for circuit designers,
especially if they are on a budget.
Why are good clocks so rare?
Most analogue interfaces can provide workmanlike performance when internally clocked, since this is
only a matter of providing a stable clock oscillator (or range of oscillators) at a fixed frequency (or
frequencies) although even this is not always well-executed. The real problem is that in many
situations an analogue interface can't operate from its own internal clocks since it must be locked to
an external reference sync. In the case of Callia, and 'asynchronous' USB interfaces in general, the
problem is alleviated in the USB input case by the interface hardware generating a local clock to
which the host computer has to synchronise. But when the unit has to lock to an external S/PDIF
input the problem returns.
The externally-clocked design challenge has traditionally been a trade-off since the more stable a
clock oscillator is, the less is its range of frequency adjustment: but we would ideally like an oscillator
which can operate over a wide range of sample rates, perhaps from <44.1kHz to >48kHz, plus
multiples thereof. But such an oscillator would inevitably have poor stability at least in terms of the
stringent requirements for high-quality audio conversion. On the other hand, if we limit the range of
rates at which the oscillator needs to operate to small ‘islands’ around the standard sample rates we
could use a bank of oscillators, selecting the appropriate oscillator according to our desired sample
rate. But this is expensive and, in any case, the 'pull-range' of an ordinary quartz crystal oscillator is
still generally insufficient to meet the tolerance demands of the digital audio interfacing standards.
As well as a very stable clock oscillator, a good sounding converter must have a PLL (phase-locked
loop) with a loop-filter which steeply attenuates incoming reference jitter towards higher frequencies.
Unfortunately, even if sourcing equipment provides a reference clock with low jitter, cabling always
adds unacceptable amounts, especially poor quality or high-capacitance cable, which results directly
in sampling jitter in the analogue interface if jitter-filtering is inadequate.
Prism Sound's unique CleverClox technology breaks these traditional constraints, allowing a low jitter
clock to be re-created from any reference sync, no matter how much jitter it has and no matter what
its frequency.
But why is clock jitter so important?