Specifications

www.ti.com Event-Trigger Submodule Registers
Table 4-27. Event-Trigger Clear Register (ETCLR) Field Descriptions (continued)
Bits Name Value Description
0 Writing a 0 has no effect. Always reads back a 0
1 Clears the ETFLG[SOCA] flag bit
1 Reserved Reserved
0 INT ePWM Interrupt (EPWMx_INT) Flag Clear Bit
0 Writing a 0 has no effect. Always reads back a 0
1 Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated
SPRU791F – November 2004 – Revised July 2009 Registers 119
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