Technical data

The FREE and CYCLE-SYNCHRONIZED modes are now explained in
more detail.
Send GP (free)
Explanation of Fig. 9.2:
In the free mode, there is no synchronization with the PLC cycle. The
consistency of the I/Os can therefore only be guaranteed for one byte. The
time at which the output byte is evaluated (i.e. the new/old comparison) is
determined solely by the CP (e.g. after sending the previous GP frame). In
the free mode, a cycle overflow of the PLC cannot be detected. A cycle
overflow means that the data of a PY were updated at least twice by the
control program before the GP was able to perform a "new/old" comparison.
PLC
program
execution
GPB I/O
area in
CP-DPR
PY7
GPB10
to the BUS
GPB
that transmits
GP
1*
100
1
100
100
5 5
100
5
5
0
0
Comparison
Comparison
Internal
cycle
Internal
cycle
Internal
cycle
* not transferred, skipped
by internal cycle
???
t
??? undefined status
Fig. 9.2: How the Mode Transmit FREE Functions
B8976060/02 Communication with Global I/Os
9 - 7 Volume 1