Technical data

Receive GP in the free mode
Explanation of Fig. 9.3:
When a frame containing changes is received, the data are entered in the
DPR independently of the PLC cycle. This means that the consistency of
the received data, just as with sending, can only be guaranteed for one
byte. In the free mode, a cycle overflow cannot be detected by the bus. A
cycle overflow means that the data of a PY from the bus were updated at
least twice before the control program was able to evaluate the PY data.
PLC
program
execution
GPB I/O
area in
CP-DPR
PY1
GPB10
from BUS
GPB
that receives
GP
0
20
0
20
20
30
20
30 30
0
???
Bus
cycle
Bus
cycle
Bus
cycle
40
40
t
??? undefinined status
Fig. 9.3: How the Mode Receive FREE Functions
B8976060/02 Communication with Global I/Os
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