Technical data

Receive GP (cycle-synchronized)
Explanation of Fig. 9.5:
The consistent acceptance of the input byte by the CP takes place at the
cycle checkpoint. The cycle checkpoint must be made known to the CP with
a handling block.
➣
At the point when the HDB is executed, all changed PYs are entered in
the DPR by the CP. Once the HDB has been executed, the PLC can
access this current data of the PY.
PLC
program
execution
GPB I/O
area in
CP-DPR
PY1
GPB10
from BUS
GPB
that receives
GP
???
0
20
HDb execution
HDB execution
60
HDB execution
0
0
20
20
60
60
20
0
tt
PLC
cycle
PLC
cycle
20
40 *
60 *
Bus
cycle
Bus
cycle
20
Bus
cycle
* cycle overrun is entered in the station list
??? undefined status
Fig. 9.5: How the Mode Receive CYCLE-SYNCHRONIZED Functions
B8976060/02 Communication with Global I/Os
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