Technical data

The following diagram illustrates how the CYCLE-SYNCHRONIZED mode
functions for input bytes.
Explanation of Fig. 11.8:
The input byte information received from the L2 bus when processing the
DP polling list is buffered by the CP after it completes the DP polling list
cycle and transferred completely to the input area of the CP with the next
HDB RECEIVE 211 call. After the "update PII" function at the beginning of
every program cycle of the CPU or by means of direct access (for example,
LPY) to the input bytes, the received data can be further processed in the
user program.
PLC
Program
PY1 : 0
Data information
received on the
L2 bus
HDB-RECEIVE
211 CALL
PY1: 0
PY1: 10
PY1: 10
HDB-RECEIVE
211 CALL
PY1: 9
PY1 : 10
PY1 : 10
PY1 : 10
PY1 : 9
PY1 : 9
Input
area
PY1 : 0
PY1 : 10
PY1 : 7
PY1 : 9
nth processing
of the DP
(n+1) processing
of the DP
in CP
polling list
polling list
Fig. 11.8 CYCLE-SYNCHRONIZED Mode: Master Receives from Slave
B8976060/02 Distributed I/Os (DP)
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