Technical data

13.5 Restrictions / Tips
The time should be read or set by the programmable controller (with
RECEIVE) at a time interval > 10 ms.
a) The hardware clock of the CP 5430 TF/CP 5431 FMS itself only has a
resolution of 10 ms.
b) By reading or setting the clock too quickly (cyclically) PLCs, the CP
5430 TF/CP 5431 FMS can be influenced to such an extent that the
module is disabled for other activities.
To avoid loading the SINEC L2 bus with unnecessary time frames, a
synchronization time greater than 10 seconds should be selected.
To ensure that the CP functions correctly, the following points must be
taken into account:
➣
The cycle time for synchronization frames on every CP 5430 TF/CP
5431 FMS must be the same. The default cycle time is 10 seconds (can
be modified in the Clock Init screen).
➣
At least one dynamic clock master must be configured.
C8976060/02 Clock Services
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