Technical data

If the CP is in a transitional status, i.e. it has not received a synchronization
frame, and is attempting to become master, then depending on the L2
address, larger deviations are possible (refer to Table 13.2). The bus
parameters are not included in these calculations. Depending on the real
CP load and parameter settings, greater deviations in the accuracy may be
possible.
❑
L2 address
Cycle time and resulting deviations in the time of day
1 s 10 s 60 s
1
2
0.55 ms/s
0.83 ms/s
3.04 ms/10s
3.32 ms/10s
16.58 ms/min
16.86 ms/min
::::
10
11
19.38 ms/min
19.66 ms/min
::::
20
21
8.36 ms/10s
8.64 ms/10s
::::
30
31
8.67 ms/s
8.95 ms/s
Table 13.2 Status Transitions
C8976060/02 Clock Services
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