Technical data

3.3 Application Interfaces of Layer 2 Communication 3 - 11
3.3.1 Explicit Communication 3 - 11
3.3.1.1 S5-S5 Communication 3 - 11
3.3.1.2 Free Layer 2 Communication with FDL Services 3 - 12
3.3.1.3 Fieldbus Management with FMA Services 3 - 14
3.3.2 Implicit Communication 3 - 15
3.3.2.1 Global I/Os (GP) 3 - 16
3.3.2.2 Cyclic I/Os (ZP), only with CP 5430 TF 3 - 17
3.3.2.3 Distributed I/Os (DP) 3 - 18
4 Technical Description and Installation of the
CP 5430 TF/CP 5431 FMS 4 - 1
4.1 Technical Description 4 - 1
4.1.1 Communications Processor CP 5430 TF/CP 5431 FMS 4 - 1
4.1.1.1 Mode Indicators (RUN and STOP LEDs) 4 - 3
4.1.1.2 Fault LED 4 - 6
4.1.2 Data Exchange between the CPU and
CP 5430 TF/CP 5431 FMS 4 - 7
4.1.2.1 Hardware Monitoring (Watchdog) 4 - 11
4.1.3 Technical Data of the CP 5430 TF/CP 5431 FMS 4 - 12
4.1.3.1 Interfaces 4 - 12
4.1.3.2 Operating and Environmental Conditions 4 - 12
4.1.3.3 Mechanical and Electrical Data 4 - 13
4.1.3.4 Logical Characteristics 4 - 13
4.1.3.5 Performance Data CP 5430 TF 4 - 14
4.1.3.6 Performance data of the CP 5431 FMS 4 - 16
4.1.3.7 Interface Assignments 4 - 18
4.2 Memory Submodules 4 - 20
4.2.1 Memory Submodule Types for the
CP 5430 TF/CP 5431 FMS 4 - 20
4.3 Installation Guidelines 4 - 21
4.3.1 Basic Configuration 4 - 21
4.3.1.1 CP 5430 TF/CP 5431 FMS Slots in the various PLCs 4 - 21
4.4 Ways of Connecting PGs on the SINEC L2 Bus 4 - 26
4.4.1 Structure and Functions of the Bus Terminal 4 - 29
Contents B8976060/02
Volume 1 II