Technical data

The interface number (SSNR)
consists of the base interface number and
the page number of the CP.
For the data exchange between the CP 5430 TF/CP 5431 FMS and the
PLC-CPU a 4 Kbyte dual-port RAM (DPR) is available which is divided into
4 pages each of 1 Kbyte.
In the address area of the CPU, the memory area F400
H
... F7FF
H
(1
Kbyte) is available for addressing the dual-port RAM of CPs/IPs with page
addressing. To allow more than one CP/IP to use this memory area to
exchange data with a CPU, the page numbers must not overlap. To ensure
a unique assignment, the pages as seen by the PLC are numbered from 0
to 255.
The CP 5430 TF/CP 5431 FMS always occupies 4 pages, beginning with
the page number assigned to it with the "base interface number" parameter.
For this reason, the base interface number beginning at 0 can only be set in
steps of 4 (0, 4, 8, 12, ..., 248).
The grouping of pages into four for the CP is only necessary with the
multiprocessor PLCs to prevent the page numbers overlapping which would
result in double addressing (refer to Fig. 4.3).
In the multiprocessor PLCs, the assignment of CPU and page number is as
illustrated in Fig. 4.3.
CPU1 CPU2 CPU3 CPU4
0123 4567
base SSNR 0
base SSNR 4
CP 1
CP 2
Multiprocessor PLCs
. . .
base SSNR 8
base SSNR 248
Fig. 4.3 Interface Addressing with a Multiprocessor PLC
B8976060/02 Technical Description and Installation of the CP 5430 TF/CP 5431 FMS
4 - 9 Volume 1