User's Manual

Page 14
SVR-200 Service Manual
Receive audio path: Receiver audio from the transceiver module is input on P2 pin 13 and presented to U5 pin
10 and pin 16. Pin 10 is the input of the receiver highpass filter to remove any sub-audible signals before being output
on pin 11 and sent to U4 for receiver audio processing. Pin 16 is the input to the sub-audible tone decoder section
of U5. Receive audio entering pin 7 of U4 is processed as flat, or -6db/octave depending upon PC programming.
The receive audio then passes through the internal lowpass filters to remove unwanted noise and output on pin 21,
where it is sent to the local receiver audio amp and mobile transmit audio output amp U1B. J1 selects either high
sensitivity (open) or low sensitivity (shorted) and J2 selects the output impedance (600/2.2K Ohms).
Sub-Audible tone signalling: U5 processes the sub-audible signal from the receiver by comparing the incoming
signal to previous samples in a noise correlator. If the signal is sufficiently coherent, the output of the comparator
is counted by the internal circuitry and an interrupt is generated to the main microprocessor. U12 reads the data
from U5 in 2 bytes: byte one contains the number of complete cycles detected within 122mS, and byte 2 contains
the number of internal clock cycles elapsed for the remainder. U12 performs a comparison of minimum and
maximum values allowed in a look up table and determines if the data is within the decode bandwidth for the
programmed tone.
In band tone signalling: Audio from the transceiver is also fed to U3B where it is amplified and limited for input
to the commutating switched capacitive filter made up by C23-C26 and P0.4-P0.7 of the microprocessor. The
microprocessor outputs four identical signals with 90° phase difference on the respective port pins. The resultant
wave form will be a function of the difference between the incoming signal frequency and the decode frequency
output by the microprocessor. The signal is buffered by U3C and amplified by U3A before being rectified and
filtered by D1 and C2. The resulting DC voltage is compared to the reference voltage by U3D. If the incoming
signal is within the decode bandwidth, the output of U3D will be a logic 1 and read by the microprocessor.
Logic and control: U12 is an Atmel 89C52 microprocessor with flash E²PROM memory. The microprocessor
provides all of the logic and control functions for the repeater including mobile/repeater PTT output, local mobile
PTT sense, mobile transmitter activity sense, audio switching, in-band & CTCSS detect, and repeater status
indications via DS4 and DS5 led arrays.
The 89C52 has four 8 bit ports that interface with the rest of the hardware on the controller board; a brief
description of each port follows:
P0.0-0.3 Channel Selector input; used only on SVR-214 version.
P0.4-0.7 These four lines make up the input to the switched capacitive filter network of C23-C26. During
receive mode, the lock tone frequency will be output on each of these lines with a 90° phase difference
between them at any given time. During transmit mode, these lines are in active and open collector.
P1.0-P1.2 LED data is output on P1.0 line every 10mSec. Data is loaded into shift register U9 8 bits at a time
and is clocked by P1.1. P1.2 latches the data into U9 for display.
P1.3 PLL latch enable output to the RF module. During transmit to receive and receive to transmit
transitions, this line is used to latch the serial data into the PLL shift registers. The serial data and clock
lines are shared with U10 (E²PROM) U4 (audio processor) and U5 (sub-audio processor).
P1.4 E²PROM chip enable, active high. Data is output to the E²PROM on P1.6 and clocked by P1.5. Data
is input from the E²PROM on P1.7. P1.4 will go active during read and write operations with U10.
U10 is written to every time the unit is programmed. U10 is read only at power up.