www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 − FIR Filter Block Consists of 16 Cells Providing up to 256 Taps Per Channel − 64 Parallel Input Bits and 64 Parallel Output Bits Provide Flexible I/O Options − Multiple Real and Complex Outputs − Two Channel Double Rate Real Output Mode With Rates to 320 MSPS − Outputs Can Be Independent, Summed Into Two or One Output(s), and Optionally Merged With Multiple GC5016 Chips JTAG Boundary Scan 3.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 1 DESCRIPTION The GC5016 is a flexible wideband 4-channel digital up-converter and down-converter. The GC5016 is designed for high-speed, high bandwidth digital signal processing applications like 3G cellular base transceiver station transmit and receive channels. The GC5016 is also applicable for general-purpose digital filtering applications.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 4 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) GC5016 Pad ring supply voltage, VPAD −0.3 V to 4 V Core supply voltage, VCORE −0.3 V to 2.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 7 AC CHARACTERISTICS −40°C to 85°C case, supplies across recommended range unless otherwise noted PARAMETER fCK tCKL tCKH tr, tf Clock frequency (1) Clock low period (below VIL) (1) Clock high period (above VIH) (1) Input set up before CK goes high (AI, BI, CI, DI, SIA, or SIB) (1) Input hold time after CK goes high (1) td th(o) Data output delay from rising edge of CK.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 9 POWER CONSUMPTION The maximum power consumption depends on the operating mode of the chip. The following equation estimates the typical power supply current for the chip. Chip-to-chip variation is typically ±5%. The AC Characteristics provides the production test limit for current in a maximum configuration. It is 10% over the typical value. Icore = (fCK/100 MHz) (Vcore/1.8 V) (Number_of_Active_Channels/4) (0.
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www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 12 TERMINAL FUNCTIONS Bit 0 is the least significant bit on all buses. All outputs are able to be put into a high-impedance state. JTAG related inputs have pull-ups if an external pulldown is used, it must be less than 500 Ω. When I and Q are multiplexed, I comes first. All clocked inputs are registered on the rising edge of CK and all clocked outputs are released on the rising edge of CK, except for Jtag output (TDO).
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 SIGNAL TYPE DESCRIPTION DATA I/O (CONTINUED) IFLG O Clocked output A flag used to indicate which samples are real or imaginary in up-conversion mode when I and Q are time multiplexed. WRMODE I A static control input that changes the timing of control writes. Normally tied low. When low control write data must be stable for a setup time ahead and hold time after the end of the write strobe.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 13.2 Receive Input Formatter (RINF) The GC5016 has four 16-bit input ports AI[15..0], BI[15..0], CI[15..0], and DI[15..0]. The formatter converts the representation of real or complex data at the input pins to a complex format output. 13.2.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 13.2.3 Receive Interpolation If the GC5016 CK rate divided by the input sample rate is an integer ratio, receive interpolation can be used (see Figure 4). In this case, the chip can be programmed to insert 0−15 zeros (rinf_zpad) between input samples. This effectively interpolates the signal up by rinf_zpad+1. The higher CK rate means the chip is operating faster, so the PFIR has more multiplication operations available per sample.
tSU tSU tH N 1 DDC Channel Data (int) 0 N 1 GC5016 Input ZPAD Counter (Int) Sync Input GC5016 CK 0 0 N+1 tH N+1 1 0 0 N+2 N+2 1 0 0 N+3 N+3 1 0 0 N+4 N+4 1 0 0 N+5 N+5 1 0 0 N+6 N+6 1 0 0 N+7 N+7 1 0 0 N+8 N+8 1 0 0 N+9 N+9 1 0 0 SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 www.ti.com Figure 4.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 13.2.4 Receiver Desensitizing In a few circumstances, it is necessary to reduce the receiver sensitivity, which can be done by adding noise to the signal. The GC5016 allows this to be done digitally by adding pseudo random noise to selected bits in the input data stream. The noise power is added by bit wise xoring the input data stream with a Pseudo-random Noise (PN) sequence.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 BI AI DI BQ CI AQ 2 DQ CQ 16 2 mix_rcv_sel TI GND mix_rcv_cmplx TQ XI GND 2 XQ 18 2 mix_qcos mix_icos mix_inv_icos mix_inv_qcos 20 20 cos real TI GND TQ XI GND 2 XQ 2 mix_isin mix_qsin mix_inv_isin 20 mix_inv_qsin 20 sin 20 21 imag Figure 5. Multiplexing Options in Mixer 13.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 Dither Generator Phase Offset 48 16 48 7 18 23 Frequency Word Sine/Cosine Lookup Table 20 Sine/Cosine Out Figure 6. Numerically Control Oscillator (NCO) Circuit The NCOs can be synchronized with NCOs on other chips. This allows multiple down converter outputs to be coherently combined, each with a unique phase and amplitude.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 NCO OUTPUT POWER vs FREQUENCY NCO OUTPUT POWER vs FREQUENCY 0 −50 NCO Output Power − dB NCO Output Power − dB 0 −107 dB −100 −150 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 −50 −121 dB −100 −150 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency − fS Frequency − fS a) Plot Without Dither or Phase Initialization b) Plot With Dither and Phase Initialization Figure 8.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 The decimated output is scaled to 24bits and input to the 5 stage comb section M=1. After the 5 comb sections, the 24bit output is scaled to 18 bits. The 18 bit output is saturated to 17 or 18 bits. The 17bit output is used when the PFIR uses symmetry. A block diagram of the decimating CIC filter is shown in Figure 9. The CIC filter has a gain equal to cic_dec5 that must be compensated for by the CIC scale circuit.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 D D D D D D An input swap RAM 15 common-programmed FIR filter cells A special 16th FIR end cell, and back-end control RAM A common control and address generator Accumulator logic An output gain shift, round, and limit block Each PFIR can process real or complex data.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 Number_of_clocks = cic_dec x fir_dec If the data stream is complex, then half the clock cycles are used computing the I output and half are used computing the Q output. The tap delay line limits the filter length to 256 if non-symmetric and 512 if symmetric (half this with complex data streams). The maximum number of taps is determined by the cmd5016 program.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 The customer software can read the power meter several times, to obtain a valid reading, or can use the handshake signals to ensure reliable power measurements. If the processor is not sufficiently aware of time and the user wishes to avoid using the handshake, it is possible to read the power meter several times in rapid succession, checking that the value is consistent. Figure 11 shows the hardware.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 Example using manual one shot firing: 1. Sync integration counter 2. Wait for ready bit to be 1 (eight clocks or less depending on sync source) 3. Arm and fire one shot to clear ready 4. Wait for ready bit to be 1 5. Read power LSB 6. Read power MSB 7. Arm and fire one shot to clear ready 8. Check to be sure missed bit is not set 9. Go to step 4 NOTE: The too_soon bit is never set if ready is active when one shot fires. 13.
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www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 The step size can be set using four values of D. The user can specify separate values of D for when the magnitude is: below threshold (agc_Dblw), above threshold (agc_Dabv), consistently equal to zero (agc_Dzro), or consistently equal to maximum (agc_Dsat). This allows the user to set different attack and decay time constants.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 The clocks [A..D]CK for each port are generated by dividing the GC5016’s main clock CK by a programmable divider for each port. Programming the divided port clock establishes the output rate for this port. The clock dividers can be synchronized by the methods described in the Synchronization section. The polarity of each divided port clock [A..
I(Q) I(Q)MSB I(Q)MSB I(Q)MSB DDC Output DDC Output DDC Output 7 DDC Output Sequence Counter (int) Channel FS Receive Output Clk Sck_div = 1 ckp_N = 1 Channel Clk Sck_div = 1 ckp_N = 0 Channel CK I(Q)MID1 I(Q)MID I(Q)LSB 6 td I(Q)MID2 I(Q)LSB 5 th(o) 3 2 1 0 BITS=16, PINS=4 BITS=20, PINS=8, OR BITS=12, PINS=4 BITS=20, PINS=16, OR BITS=16,12,PINS=8, OR BITS=8, PINS=4 BITS=16, PINS=16, OR BITS=8,PINS=8, OR BITS=4, PINS=4 I(Q)LSB 4 Decimation = 16 I(Q)MSB I(Q)MSB I(Q)MSB I
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 The frame strobes [A..D]FS are used to signify the beginning of a data frame for each port. The frame strobes are set high by the GC5016 with the first word in a frame. The GC5016 output can be a single data, interleaved complex data, or time division multiplexed data. The GC5016 may be configured to have one port for each channel.
IMSB IMSB IMSB DDC Output DDC Output I 7 DDC Output DDC Output Sequence Counter (int) Channel FS Receive Output Clk Sck_div = 1 ckp_N = 1 Channel Clk Sck_div = 1 ckp_N = 0 Channel CK IMID1 IMID ILSB Q 6 td IMID2 ILSB QMSB 5 th(o) QMSB ILSB 2 1 0 BITS=16, PINS=16, OR BITS=8,PINS=8, OR BITS=4, PINS=4 3 QMSB QMID QMID1 BITS=16, PINS=4 QLSB QMID2 BITS=20, PINS=8, OR BITS=12, PINS=4 QLSB BITS=20, PINS=16, OR BITS=16,12,PINS=8, OR BITS=8, PINS=4 QLSB 4 Decimation = 16
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 13.12.1 Multichannel Time Division Multiplex Two or four channels can share one output port, with the data for each channel time multiplexed. In this case, the frame strobe is set high with the MSB in the first I word in the frame as shown in Figure 15. The number of pins used for a port is user programmable as 4, 8, or 16 , and the number of bits in a word is user programmable as 4, 8, 12, 16, or 20. 13.12.
DDC Output DDC Output DDC Output Sequence Counter (int) Channel FS Receive Output Clk Sck_div = 1 ckp_N = 1 Channel Clk Sck_div = 1 ckp_N = 0 Channel CK CH4I(D) CH2Q(D)MSB CH2Q(D) 7 CH4Q(D) CH2Q(D)LSB CH2I(C) 6 td CH3I(C) CH2Q(C)MSB CH1Q(B) 5 th(o) 3 1 SPLITIQ=1, BITS=16, PINS=16 2 0 CH1Q(B)LSB CH1I(A)MSB CH1I(A)LSB CH3Q(C) CH2I(B) CH2Q(B) CH1I(A) CH1Q(A) SPLITIQ = 0, AND ( (BITS=16,PINS=16) OR (BITS=8, PINS=8)) CH1Q(B)MSB SPLITIQ=1 AND ((BITS=20, PINS=16) OR (BITS=16,
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 13.13 Overall Gain in Receive Mode The overall gain in the receive mode is a function of zero padding (rinf_zpad), the CIC decimation (cic_dec), the cic shift settings (cic_shift and cic_rshift), the sum of the programmable filter taps (PFIR_SUM), the filter output shift (fir_shift) and the final gain in the agc circuit (G).
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 14 GC5016 DIGITAL UP CONVERSION (DUC) MODE The GC5016 can be configured as a digital up converter (DUC). The DUC interpolates, filters, mixes, and sums the customer inputs into one or several output ports. The GC5016 DUC (See Figures 2 and 16) has several blocks: Transmit Input Interface Gain PFIR CIC Mixer Sum, SumIn, and Transmit Output Formatter The GC5016 has either four independent DUC channels, or two Wideband (split IQ) DUC channels.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 The double rate DUC mode utilizes the splitIQ mode with special CIC filter special mixer, and special output port programming. The double rate mode has two output ports versus one, as there are even and odd DUC outputs. The CIC filters produce even and odd sample outputs at the CK rate. The cmd5016 software keyword ’toutf_rate 2’ controls the double rate mode, 14.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 The sck_div can be used to program the GC5016 receive data every second, third, etc., clock edge, allowing the data source to supply data at a lower speed. The user controls the clock division using sck_div. A value of 0 means that every clock edge is used; a value of 1 means that every other clock edge is used, etc. The clock division phasing is controlled by a general sync (sck_sync).
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 Transmit Input Mode TDM(not splitiQ) IQ Data TDM(splitiQ) IQ Data TDM(parIQ, splitiQ) Bits Pins Port Pins Used Number of Divided Clocks for I and Q, or I 20 16 15..0 8 16,12 16 15..0 4 20 8 15..8 24 16,12 8 15..8 16 8 8 15..8 8 20 4 15..12 40 16 4 15..12 32 12 4 15..12 24 8 4 15..12 16 20 16 15..0 8 16,12 16 15..0 4 20 8 15..8 12 16,12 8 15..8 8 8 8 15..8 4 20 4 15..
I(Q) I(Q)MSB I(Q)MSB I(Q)MSB AIn[ ] AIn[ ] AIn[ ] tinf_fs_dly = 1 AIn[ ] AFS ck_pol = 1 Sck_Div=1 ACK Sck_Div=1 CK ACK I(Q)MID1 I(Q)MID I(Q)LSB I(Q)MID2 I(Q)LSB I(Q)LSB Interpolation Ratio = 24 BITS=16, PINS=4 (BITS=20, PINS=8) OR ( BITS=12, PINS=4) (BITS=20, PINS=16) OR (BITS=12,16, PINS=8) (BITS=16, PINS=16) OR (BITS=8, PINS=8) I(Q)MSB I(Q)MSB I(Q)MSB I(Q) I(Q)MID1 I(Q)MID I(Q)LSB I(Q)MID2 I(Q)LSB I(Q)LSB www.ti.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 14.2.5 8bit IQ Parallel The GC5016 may also be configured to accept input data with 8 bits of I and 8 bits of Q in parallel. I MSB should be placed at AI[15] and Q MSB at AI[7] (or BI, CI, or DI). This mode is valid only for 8-bit I and 8-bit Q using 16 pins. Applications with fewer bits usually connect the unused bits to GND. 14.2.
CK AI(MSB) AIn[ ] AI AI tinf_fs_dly = 1 AIn[ ] AIn[ ] AFS ck_pol = 1 Sck_Div=1 ACK Sck_Div=1 ACK AI(LSB) AQ AQ BQ BQ AQ(MSB) AQ(LSB) BI BI BI(MSB) CI BI(LSB) CQn DQn AI BQ(MSB) BQ(LSB) AI(MSB) AQ AQ AI(LSB) SPLITIQ = 1 AND ( (BITS=20, PINS=16) OR (BITS=16,12, PINS=8)) AI SPLITIQ = 1 AND ( (BITS=16, PINS=16) OR (BITS=8, PINS=8)) DIn SPLITIQ = 0 AND ( (BITS=16, PINS=16) OR (BITS=8, PINS=8)) Interpolation Ratio = 24 AQ(MSB) BI BI AQ(LSB) BQ BQ www.ti.
ACK CK I IMSB IMSB IMSB AIn[ ] AIn[ ] AIn[ ] tinf_fs_dly = 1 AIn[ ] AFS ck_pol = 1 Sck_Div=1 ACK Sck_Div=1 IMID1 IMID1 ILSB Q IMID2 ILSB QMSB ILSB QMSB QLSB QMSB QMID QMID1 QLSB (BITS=16, PINS=16) OR (BITS=8, PINS=8) QMID2 QLSB BITS=16, PINS=4 (BITS=20, PINS=8) OR ( BITS=12, PINS=4) (BITS=20, PINS=16) OR (BITS=12,16, PINS=8) Interpolation Ratio = 24 IMSB IMSB IMSB I IMID1 IMID1 ILSB Q IMID2 ILSB QMSB ILSB QMSB QLSB SLWS142J − JANUARY 2003 − REVI
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 14.3 Gain Each 20-bit input sample is multiplied by a 19-bit gain word. The 16 gain LSB’s are stored in one register, gain_lsb and three MSB’s in another, gain_msb. The gain adjustment is GAIN/212, where the gain word (gain) ranges from 0 to (+219 − 1). Negative gains are not allowed. This gives a 0.002-dB gain adjustment resolution. Setting gain_msb and gain_lsb to zero clears the channel input.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 The PFIR coefficients are programmed through the cmd5016 configuration software, based on the number of filter taps computed per clock cycle, the number of clock cycles per output, the number of data streams in the PFIR channel, the symmetry of the filter taps, and the number of filter taps. The mode_ab(cd), splitiq, cic_int, fir_int, fir_diff, fir_nchan, and pfir_coef tap filename are the cmd5016 inputs.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 NOTE:If overall-gain is not used, and if the gain is set too high, then the signal can overflow internally, which causes CIC instability. A momentary high power noise spike is seen on the output before the autoflush forces the CIC to zero. If the gain is set so high that the signal rapidly overflows internally, the output appears as a pulsing signal as the CIC periodically overflows.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 NCO AI AFS ACK TINF GAIN PFIR Dual CIC IFLG B TDM Broadcast C SUM and FORMAT AO [15:0] BO [15:0] CO [15:0] DO [15:0] D Figure 22. Normal Mode Transmit Channel 14.6.1 splitIQ Mode The SplitIQ mode uses channels A,B and C,D in pairs. The PFIR and CIC are used with real data into channel A or C, and imaginary data into channels B or D. Figure 22 shows the standard configuration.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 NCO I(2k) Real In AI AFS ACK TINF GAIN PFIR I(2k) Q(2k) Dual CIC I(2k+1) TDM Broadcast Cross connect for double rate IFLG SUM and FORMAT NCO Q(2k) Imag In BI BFS BCK TINF GAIN PFIR AO [15:0] BO [15:0] CO [15:0] DO [15:0] I(2k+1) Q(2k+1) Dual CIC Q(2k+1) C D Figure 23. Double Rate Mode Transmit Channel 14.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 D Using the split IQ mode that merges channels A and B together to give more taps (split_IQ=1). D Using the double rate output mode (tout_rate=2). The output from the transmit output format block can be rounded to 12, 14, 16 or 22 bits using the toutf_rnd_AB control for the AO and BO ports, and toutf_rnd_CD control for the CO and DO ports. The settings are ”3” for 12 bits, ”2” for 14 bits, ”1” for 16 bits and ”0” for 22 bits.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 Table 3.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 14.9 The Sum Tree Figures 24 and 25 show the sum tree and transmit output format blocks when all four channels are added together, including the sum IO path. Figure 24 shows the data paths for the standard 16 bit resolution mode (tout_res=0). Figure 25 shows the wide resolution mode (tout_res=1). The mixer outputs are rounded to 21–bits.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 Sum In Sum Tree 21 I Channel A Q 22 21 22 21 I Channel B Q 21 21 I Channel C 23 23 Shift Down by 4 and Round 19 22 19 22 Upshift 0−7 and Limit Transmit Output Formatter sum_shift Q 21 21 I Channel D Q 21 Figure 25. Sum Tree and Transmit Output Formatter − 22-Bit SumIO Mode 14.10 Sum and Format Details Figure 26 shows the sum and format blocks in more detail.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 DO CO sumin sum_shift a ia Asum b sum_ia Mux, Round sum_selI AO c qa Bsum d sum_ib a ib Asum b sum_qa Mux, Round sum_selQ BO c Bsum qb d sum_qb toutf_rnd_AB toutf_halfcmplx_AB toutf_quiet_AB Mux, Round, Delay Mux, Round, Delay toutf_rnd_CD toutf_halfcmplx_CD toutf_quiet_CD Transmit Output Mux ic CO id DO toutf_bo toutf_co toutf_do toutf_hold toutf_offsetbin Figure 26. Transmit Sum and Output Format Details 14.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 Table 4. Sum Selection Settings Sum_sel setting Asum Bsum 0x0 0 0 0x43 a b 0xA7 a+b c+d 0xB7 a+b+c+d c+d 14.10.2 Sumin Port for Cascading Chips If sumin is active, the ports CO and DO are used as inputs (reducing the number of outputs available). The control sumin determines the format of the sum in port data. Both outputs are forced to zero when sumin=0. When sumin = 1, a 22-bit half-rate complex sumin path is formed.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 14.10.4 Output Rounding and I/Q Multiplexing The data on paths A and B next enter mux and round. Multiplexing allows I and Q to be time multiplexed onto the same set of pins. Effectively, this decimates the signal by two and the sync source for this decimation is the cic_sync. Finally, toutf_rndAB controls rounding of bits from the bottom, so the resulting word is 12 (3), 14 (2), 16 (1), or 22 (0) bits.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 15 GC5016 IN TRANSCEIVER MODE The GC5016 can also be configured in a transceiver mode as shown in Figure 3, where channels A and B function in up-conversion mode and channels C and D function in down-conversion mode. The channel details for A and B are identical to those described above for the up-conversion mode. The channel details for C and D are identical to those above for down-conversion mode.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 16.2 Dual Strobe, Edge Mode(WRMODE = 0), Control Bus Timing (See Figures 27 and 28) In this mode, an external processor (a microprocessor, computer, or DSP chip) can write into a register by setting A[4..0] to the desired register address, setting RD high, selecting the chip by setting CE low, then strobing WR low. The write cycle is active while both CE and WR are low. Data on the C[15..0] is registered into the chip on the rising edge of WR.
www.ti.com ÓÓÓÓ ÓÓÓÓ ÓÓÓÓ ÓÓÓÓ ÓÓÓÓ ÓÓÓÓ ÓÓÓÓ SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 CE tREC WR tsu(C) tCSPW RD ÔÔÔ ÔÔÔ ÔÔÔÔ ÔÔÔÔ ÔÔÔÔ ÔÔÔÔ ÔÔÔÔ A [4:0] th(C) C [15:0] WRITE CYCLE − NORMAL MODE tsu(EWC) Figure 28. Dual Strobe Edge Mode Write Timing 16.3 Single Strobe, Edge Mode(WRMODE = 0), Control Bus Timing (See Figures 29 and 30) Some processors provide a single control RD/WR together with a chip strobe that controls timing. In this case, the RD pin can be grounded.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 CE ÓÓÓÓÓÓÓ ÓÓÓÓÓÓÓ ÓÓÓÓÓÓÓ tCSPW tREC WR tsu(C) A [4:0] td(C) t(CZ) C [15:0] READ CYCLE − RD HELD LOW Figure 29. Single Strobe Read Timing CE tCSPW ÓÓÓÓÓÓÓÓ ÓÓÓÓÓÓÓÓ ÓÓÓÓÓÓÓÓ ÓÓÓÓÓÓÓÓ ÓÓÓÓÓÓÓÓ ÔÔÔ ÔÔÔ ÔÔÔ ÔÔÔ ÔÔÔ tREC WR tsu(C) A [4:0] th(C) C [15:0] WRITE CYCLE − RD HELD LOW tsu(EWC) Figure 30.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 16.4 Dual Strobe, Latch Mode(WRMODE = 1), Control Bus Timing (See Figure 31) Latch mode (WRMODE=1) is used if the data is stable over the entire time period the write strobe is active. The data on C[15..0] is transferred to the control registers during the entire time both WR and CE are low.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 16.5 Single Strobe, Latch Mode(WRMODE = 1), Control Bus Timing (See Figure 32) The user can also use the latch mode with a single strobe, as shown in Figure 32. CE WR ÓÓÓÓÓÓÓ ÓÓÓÓÓÓÓ ÓÓÓÓÓÓÓ ÓÓÓÓÓÓÓ ÓÓÓÓÓÓÓ tCSPW tREC tsu(C) ÔÔÔ ÔÔÔ ÔÔÔ ÔÔÔ ÔÔÔ A [4:0] tsu(EWC) th(C) C [15:0] WRITE CYCLE − RD HELD LOW Figure 32. Single Strobe Latch Mode Write Timing 16.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 In the Up Conversion process, the sck_sync, pfir filter, cic filter, and toutf_hold_sync will typically require synchronization. The sck_sync is used to synchronize the divided clock. The fir_sync is used to synchronize the PFIR. The coef_sync is used to synchronize switching between two banks of coefficients. The cic_sync and fir_sync need to be selected to a common sync signal.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 It is important that the synchronization source has an active SYNC signal when the Reset signal is released during the initial GC5016 programming. Repetitive synchronization, if used, requires a logic low Sync input that is one CK period wide. The cmd5016 programming software has a pseudo-command ’sync_mode’. The sync_mode is used to set up common synchronization modes for all of the sync registers.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 16.9.2 Multiple GC5016 Chips Using SO From a Master GC5016 Chip This procedure works if multiple GC5016 chips need to be synchronized. This assumes that the sync output pin (SO) from the master GC5016 chip is connected to the SIA input pin on all GC5016 chips including the master chip. 1. Reset the chip by writing 0xFF00 to address 0 of all chips. 2. Disable all outputs except SO, by writing 0x100 to address 3 of all chips. 3.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 16.10 Diagnostics The GC5016 provides self-test capability by providing a pattern generator at the inputs, a specific signal processing setup condition, a linear feedback shift register LFSR to develop an output results, and a checksum register read by the local bus. A general timer is used to sequence the load, run for n cycles, and capture the test results. The diagnostic tests are provided in the gc5016 developer’s toolkit.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 17 CMD5016 − CONFIGURATION SOFTWARE The cmd5016 is a configuration software program used to calculate the register variable values and the initialization sequence required for the GC5016. The TI Developer toolkit has the cmd5016.exe program, and a cmd5016 user’s guide for programming the GC5016 through the cmd5016 software. NOTE:The GC5016 is intended to be programmed through the supplied cmd5016 interface.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 Variables can have different types in transmit and receive mode. For example, the CIC interpolation (cic_int) is mandatory in transmit and unused in receive. Any variable may be directly set by the user and that value is used both to program the chip and in some cases to compute other fields. A user should first let the software generate values for computed and expert fields before attempting to modify them.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 Rcv Xmt TYPE DEFAULT DESCRIPTION D D splitiqAB NAME channel pair 0 If set, channel A and B are splitIQ mode, I data is processed in ChA, the Q data is processed in ChB. D D splitiqCD channel pair 0 If set, channel C and D are splitIQ mode, I data is processed in ChC, the Q data is processed in ChD. D D splitiq global 0 If set, complex IQ data is split so the I data goes to one filter and Q data goes to another.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 17.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 Table 10.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 Table 12 lists the control registers for cicAB. Table 12.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 17.5 Global Registers The following tables describe the various bit fields contained in each of the global control registers. Table 14. Global Register Reset and Clock Control Address 0x0 Bits 15.8 Set at Power Up Rcv Tx FIELD BITS Dflt DESCRIPTION − − ck_loss_status 1..0 D D en_ck_loss 8 C C pwr_dwn_fir_A 9 Power down PFIR in A. Power down puts the GC5016 section in reset and disables the clock.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 17.6 FIR Control RAMs The programmable filter has three RAM’s used to control its operation. PAGE ADDRESS REGISTER DESCRIPTION 0−F 10−1F FIR coefficients 10 10−1F Swap ram address index 11 10−1F BE ram Bit Map The filter coefficients are stored in a 16-word (by 16 bit) RAM, in each of 16 filter cells. The coefficients are 16-bit two’s complement. The coefficients can be read without interrupting normal operation.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 17.9 Programmable FIR, Gain, Transmit Input, and Receive Output Control Registers The following tables detail the various control registers for a single PFIR filter. Note that the configuration software calculates these registers. The PFIR has several sets of memories that are synchronized to read the data to be filtered, and the coefficient memory.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 Table 23. Backward Read Address Generator Page 0x12 Address 0x14 Rcv Tx FIELD BITS Dflt DESCRIPTION E E bragen_soff 3..0 FIR backward read address generator offset E E bragen_srecr 7..4 FIR backward read address generator recirculate count E E bragen_sdepd 11..8 FIR backward read address generator depth count E E bragen_stepn 15..12 FIR backward read address generator step Table 24.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 17.10 Transmit Input Formatter Controls The Transmit Input Formatter section is used to set the mode of the Transmit Input logic, control the Frame Strobe timing in Transmit mode, and to control the time when the customer logic − Transmitter input(s) are sampled. Table 30. Transmit Input Formatter Page 0x13 Address 0x10 Rcv Tx X C tinf_bits FIELD 2..0 BITS Dflt Bits per word 0 − quiet, else bits = 4 x tinf_bits.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 Table 36. AGC Maximum Adaptation Limit Page 0x13 Address 0x16 Rcv Tx D D FIELD agc_max BITS Dflt 15..0 0 DESCRIPTION AGC maximum adaptation limit. Upper limit for adapted gain is manual_gain + agc_max Table 37. AGC Counts and Threshold Page 0x13 Address 0x17 Rcv Tx FIELD BITS Dflt D D agc_zero_cnt 3..0 0 Run of zeros before fast adaptation gain increase step Dzro is used DESCRIPTION D D agc_sat_cnt 7..
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 Table 43. Power Meter Integration Time Page 0x13 Address 0x1D Rcv Tx FIELD BITS Dflt D D pwr_mtr_integ 15..0 0 DESCRIPTION Power meter integration time in words 17.13 DDC Receive Output Formatter Controls The output modes TDM, interleavedIQ, parallel IQ, or embedded gain and IQ are controlled from table 44.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 Table 47. FIR Accumulator Controls Page 0x14 Address 0x11 Rcv Tx FIELD BITS E E E E E Dflt DESCRIPTION E acc_dly 3..0 FIR accumulator delay minus 1 E acc_cnt 7..4 FIR number of partial products to accumulate E acc_dly0 8 FIR no accumulator delay (1) or not (0) E acc_bypass 9 FIR accumulator bypass (1) or normal (0). Must also set acc_cnt to zero for bypass. E acc_enram 10 FIR enable accumulate ram (1) normal.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 17.16 CIC and MIXER Control Registers There are two cicmix blocks. The blocks are arranged as channel AB and channel CD: page 0x80, addresses 0x10−0x17 channel A, page 0x80, addresses 0x18 to 0x1F channel B, page 0xA0, addresses 0x10−0x17 channel C, page 0xA0, addresses 0x18 to 0x1F channel D. Table 52 and 59 lists the CIC controls. The cic_shift, cic_rshift, cic_rcv_full, are the cic gain controls.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 Table 57. Mixer Page 0x80 Address 0x15 Rcv Tx FIELD BITS Dflt DESCRIPTION M X mix_rcv_sel 1..0 Mixer input selection in receive (paths a, b, c, or d for 0, 1, 2, or 3 respectively). C X mix_rcv_cmplx 2 Set for receive complex input at full rate or double rate. C C mix_inv_qsin 4 Invert the output of Qdata by sin in the mixer. C C mix_qsin 6..
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 Table 61. Sum Tree Multiplexing Page 0x81 Address 0x11 Rcv Tx FIELD BITS Dflt DESCRIPTION X C sum_shift 2..0 Upshifts sum before output (0−7). X C sum_ia 4..3 Summing mode off (0), 22 bit sumin (1), bypass (2), 16 bit sumin (3) X C sum_ib 6..5 Summing mode off (0), 22 bit sumin (1), bypass (2), 16 bit sumin (3) X C sum_qa 8..
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 17.20 General Timer Table 67. General Timer Page 0xA1 Address 0x11 Rcv Tx FIELD BITS Dflt DESCRIPTION D D gen_timer 15..0 65535 General-purpose timer. A 24-bit counter. The bottom eight bits of the count value are normally assumed to be zero. Timer counts down from 256 x (gen_timer + 1) to zero, then repeats.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 18 5016 − CONFIGURATION SOFTWARE 18.1 CDMA2000 This section describes an example of the down-conversion filter response for CDMA2000 1X. The GC5016 configuration values were input sample rate of 78.643 MSPS, CIC decimation of eight, and PFIR decimation of four for an overall decimation of 32, output rate of 2.4576 MSPS (2x chip rate), and 255 PFIR taps.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 18.2 WCDMA (UMTS) This section describes an example of the down-conversion filter response for WCDMA. The GC5016 configuration values were input sample rate of 122.88 MHz, a CIC and PFIR decimation of four each for an overall decimation of 16, output rate of 7.68 MSPS, and 255 PFIR taps. The overall filter response filter, including both the CIC and PFIR filters, an optimized raised root cosine filter with α = 0.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 APPLICATION INFORMATION 19 BOARD BRING-UP PROCEDURE This section describes a recommended procedure for checkout of a board using the GC5016. The various test files are available on the website. 19.1 JTAG The 1.8-Vdc VCore and 3.3-Vdc VPad should be within nominal values before using the JTAG or the Control Bus. The TRST JTAG signal is a logic ’1’ for JTAG testing. The TRST JTAG signal is a logic ’0’ for nominal operation.
www.ti.com SLWS142J − JANUARY 2003 − REVISED AUGUST 2007 The user should configure the chip as specified in the configuration file, wait the recommended time, and then read the checksum results and compare them to the expected results shown in Table 73. Table 73. Expected Checksum Results Configuration Name Wait Time (in clocks) Expected Results Transmit Chan A Chan B Chan C Chan D TCK10R0.GC101 4,000,000 0x121D − − − − TCK100R0.GC101 4,000,000 0x61EF − − − − RCK100R0.
PACKAGE OPTION ADDENDUM www.ti.com 14-Sep-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty GC5016-PB ACTIVE BGA GDJ 252 90 TBD Call TI Level-3-220C-168 HR GC5016-PBZ ACTIVE BGA ZDJ 252 90 Pb-Free (RoHS) SNAGCU Level-3-260C-168 HR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
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