Specifications

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SLWS142J − JANUARY 2003 − REVISED AUGUST 2007
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10
12 TERMINAL FUNCTIONS
Bit 0 is the least significant bit on all buses. All outputs are able to be put into a high-impedance state. JTAG related
inputs have pull-ups if an external pulldown is used, it must be less than 500 Ω. When I and Q are multiplexed, I comes
first. All clocked inputs are registered on the rising edge of CK and all clocked outputs are released on the rising edge
of CK, except for Jtag output (TDO). It is recommended that TRST have a user controlled pull-down. This input must
be a ’1’ for JTAG testing, and is recommended to be ’0’ for normal operation.
SIGNAL TYPE DESCRIPTION
CONTROL I/O
A[4..0] I Control address bus – Active high inputs
These pins are used to address the control registers within the chip. Each of the control registers within the chip are
assigned a unique address. A control register can be written to or read from by having the page register set to the
appropriate page and then setting A[4..0] to the register’s address.
C[15..0] I/O Control data I/O bus – Active high bidirectional I/O pins
This is the 16-bit control data I/O bus. Control registers are written to or read from through these pins. The chip drives
these pins when CE is low, RD is low, and WR is high.
CE I Chip enable – Active low input pin
This control strobe enables the read or write operations.
WR I Write enable – Active low input pin
The value on the C[15..0] pins is written into the register selected by the A[4..0] and page register when WR and CE are
low.
RD I Read enable – Active low input pin
The register selected by A[4..0] and the page register is output on the C[15..0] pins when RD and CE are low.
DATA I/O
AI[15..0] I Clocked input port A, data bits 0 through 15
Can be configured for many possible input formats.
BI[15..0] I Clocked input port B, data bits 0 through 15
Can be configured for many possible input formats.
CI[15..0] I Clocked input port C, data bits 0 through 15
Can be configured for many possible input formats.
DI[15..0] I Clocked input port D, data bits 0 through 15
Can be configured for many possible input formats.
AO[15..0] O Clocked output port A, data bits 0 through 15
Can be configured for many possible output formats.
BO[15..0] O Clocked output port B, data bits 0 through 15
Can be configured for many possible output formats.
CO[15..0] I/O Dual function:
Clocked output − port C, data bits 0 through 15
Can be configured for many possible output formats.
Clocked input – Sum IO input data, data bits 0 through 15
Can be configured for many possible input formats.
DO[15..0] I/O Dual function:
Clocked output − port D, data bits 0 through 15
Can be configured for many possible output formats.
Clocked input – sum IO input data, data bits 0 through 15
Can be configured for many possible input formats.
[A..D]CK O Clocked output for ports [A..D]
The clock for input ports in up-conversion mode and output ports in down-conversion mode. When configured as a
transceiver, channels A and B are in up-conversion and channels C and D are in down-conversion mode.
[A..D]FS O Clocked output frame strobes for channels A..D
Used to signify the beginning of a data frame for each input port in up-conversion mode and output in down-conversion
mode. The frame strobes are set high by the GC5016 with the first word in a frame. The frame strobes can be programmed
to be sent early.
CK I Main input clock. The clock input to the chip.