Specifications

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SLWS142J − JANUARY 2003 − REVISED AUGUST 2007
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11
SIGNAL DESCRIPTIONTYPE
DATA I/O (CONTINUED)
IFLG O Clocked output A flag used to indicate which samples are real or imaginary in up-conversion mode when I and Q are time
multiplexed.
WRMODE I A static control input that changes the timing of control writes. Normally tied low. When low control write data must be
stable for a setup time ahead and hold time after the end of the write strobe. When high data must be stable for a setup
time ahead of the write strobe going active until a hold time after it goes inactive.
RST I Chip reset bar. Active low signal. Not clocked. RST requires an external pull-up resistor or connection to VCOR Power
Monitor “1” is OK.
SIA I Sync input A bar. Active low data input signal. SIA requires an external pull-up resistor if not used.
SIB I Sync input B bar. Active low data input signal. SIB requires an external pull-up resistor if not used.
SO O Sync output bar. Active low data output signal
JTAG I/O
TCK I JTAG clock – Active high input. Internal pullup
TDI I JTAG data in – Active high input clocked on TCK rising. Internal pullup
TDO O JTAG data out – High-impedance state output clocked on falling edge of TCK.
TMS I JTAG interface – Active high input clocked on TCK rising. Internal pullup
TRST I Asynchronous JTAG reset bar. Internal pullup
SUPPLIES
GND Ground
VCOR
(1)
Core supply voltage. Used to supply the core logic, nominally set to 1.8 V.
VPAD
(1)
Interface voltage. Used to set the I/O levels for all pins, nominally set at 3.3 V.
(1)
The VCore and VPad must both be powered before programming the GC5016 Control Bus. There is no required power sequence.
The recommendation is to power VCore before or simultaneously with VPad.
13 GC5016 DOWN-CONVERSION MODE
13.1 Overview
Figure 1 shows the functional block diagram for the GC5016 when configured as a 4-channel digital
down-converter(DDC). In a common configuration, each down-conversion channel demodulates ADC sampled data
down from an IF frequency to 0Hz, low pass filters the signal data, reduces the signal rate (decimation), and outputs
I and Q baseband data. The baseband signal is measured by the Power Meter, and a gain or gain + automatic gain
are applied to the IQ data. Several output formats are available for transmitting the IQ outputs.
The DDC input can be configured for real or complex inputs. The input data on ports AI[15..0], BI[15..0], CI[15..0],
are converted to a complex input format in the Receive Input Formatter (RINF).
The Mixer stage provides the Receive Input channel selection (RSEL), digital oscillator (NCO), and complex mixing
logic (mixer) to translate the input down to 0 Hz.
After the Mixer, the 5 stage Cascade Integrator Comb (CIC) provides complex filtering and decimation. The CIC
decimation is an integer value from 1 to 256. Special logic is used for double rate processing.
After the CIC complex filter, the Programmable Finite Impulse Response (PFIR) filter provides CIC correction,
spectral shaping, and further decimation. The PFIR decimates from 1 to 16.
The PFIR complex output is measured by the Complex Power Meter. The Power Meter integrates the IQ power. The
time integrated value can be read through the Microprocessor port.
The PFIR complex output is gain (manual + adaptive) scaled.An automatic gain (adaptive gain) is computed based
on the current IQ output level. The gain scaled output is rounded to a desired number of bits resolution, and is
formatted for the DDC output.
Channels can be synchronized to support beam forming or frequency hopped systems. Two channels can be
operated in tandem to allow double input bandwidth, double output bandwidth, or both.