SLWS142J − JANUARY 2003 − REVISED AUGUST 2007
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14
GC5016
CK
GC5016
Input
ZPAD
Counter
(Int)
Sync
Input
01 01 01 01 01 01 01 01 01 01 01
DDC
Channel
Data
(int)
N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9
N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9
00000000 00
t
SU
t
H
t
SU
t
H
Figure 4. DDC Input Timing Diagram
