Specifications

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SLWS142J − JANUARY 2003 − REVISED AUGUST 2007
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The decimated output is scaled to 24bits and input to the 5 stage comb section M=1. After the 5 comb sections, the
24bit output is scaled to 18 bits. The 18 bit output is saturated to 17 or 18 bits. The 17bit output is used when the
PFIR uses symmetry. A block diagram of the decimating CIC filter is shown in Figure 9.
The CIC filter has a gain equal to cic_dec5 that must be compensated for by the CIC scale circuit. and the scale circuit
must limit the peak signal gain from the rinf_zpad, mixer, and through the CIC to be 1 or less. The peak gain is:
peak gain = (1/(1+rinf_zpad)) × (mixer_gain) × (cic_dec^5 × 2^(cic_shift−39))
The cmd5016 program will set the gain properly if the overall-gain keyword is used.
The register field cic_sync controls the precise moment of decimation. The sync can be periodic at any multiple of
cic_dec without disturbing the processing. If sync is held active, the CIC freezes its output.
The output of the CIC can be attenuated in gain by 6 dB by clearing cic_rshift. This is appropriate only when cic_shift
has been set to zero, the signal gain to this point is greater than 0.5, and symmetry is being used in the PFIR filter.
In other words, cic_rshift should almost always be set to one. The rshift_gain is 2
cic_rshift−1
.
The CIC output data feeding the PFIR must be limited to half scale if the PFIR is using symmetry. Control bit field
cic_rcv_full must be cleared in this case. If the PFIR is not using symmetry, the data is limited to full scale and the
bit field cic_rcv_full should be set to one. The CIC gain is adjusted by the cmd5016 configuration software.
When the PFIR filter is in the normal IQ interleaved mode, the CIC filter output rate must not exceed CK/2.
The splitiq pseudo-command is used to determine the PFIR filter interleaved−IQ or non interleaved mode.
Data In
CIC Scale
Decimate by cic_dec
+ + + + + − − − − −
Data Out
Figure 9. 5-Stage CIC Decimate Filter
splitIQ Mode
In some cases, a signal that is input to the chip at CK rate needs to have more filtering capacity than the chip provides
in a single channel. As noted above, twice the filtering capacity is available if each filter only processes I or Q rather
than both I and Q. The splitIQ mode programs the I data to firA or firC, and the Q data to firB or firD. Data is mixed
in mixA/C (mixB/D are idle). This is set automatically by the cmd5016 software by setting splitiq to one.
It can be set manually by setting cic_rcv_cross in cicB, programming mixB to idle, and programming firA and firB to
process real signals.
CIC in Double Rate Mode
Each channel contains two CIC filters (one for I and one for Q) allowing the input sample rate to equal the clock rate
(ck). Double rate processing allows input rates of twice this. In this case, the dual CICs in each channel can be
configured to perform as a single CIC at double rate. Thus, channel A’s CIC can process the I portion of a double
rate signal. The time samples (2k+1) come from the I portion of mixer B and are routed to CIC A using the cross
receive input (cic_rcv_cross). Likewise, channel B’s CIC processes the Q portion of a double rate signal getting time
samples (2k) from the Q portion of mixer A using the cross receive input.
When data is input at 2x rate, the CIC must decimate by at least 2 and by an even number. The cmd5016 software
uses the rin_rate pseudo-command to identify this mode. When operating in double rate mode cicA outputs I data
only to firA, while cicB outputs Q data to firB. Likewise for C and D when they are operating in double rate mode. This
means the PFIRs are operating on real data only (splitiq mode).
13.7 Programmable Finite Impulse Response Filter (PFIR)
The decimating PFIR filter consists of: