Specifications

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SLWS142J − JANUARY 2003 − REVISED AUGUST 2007
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The customer software can read the power meter several times, to obtain a valid reading, or can use the handshake
signals to ensure reliable power measurements. If the processor is not sufficiently aware of time and the user wishes
to avoid using the handshake, it is possible to read the power meter several times in rapid succession, checking that
the value is consistent. Figure 11 shows the hardware.
uP Reg
Integration
Timer
(16 Bits)
17
12
8
20
24
6
32
Figure 11. Power Meter Hardware
A ”done” control bit is set in the power meter status register when the integration counter is synchronized
(pwr_mtr_sync) and again when it reaches terminal count (pwr_mtr_integ). The ”done” signal that comes from
syncing the integration counter should be discarded. Using the periodic sync counter to sync the integration counter
is not recommended. On done, the accumulator value is strobed into the registers (page 0x13 address 0x1a and
0x1b), the ready bit (page 0x13 address 0x1c bit 15) is set, and the accumulator is cleared. Note that there are four
independent power meters. The addresses here are for channel A . Channels B, C, and D are at the same address
but on page offsets of 0x20, 0x40, and 0x60 respectively.
The control bus and system clock are at different rates. In most cases, the system clock is faster. To get the control
bus to the system clock domain, a one shot is used. Firing the one shot clears the ready bit and lets the chip know
the power was read. There are two ways to fire the one shot. It may be done automatically, when the msb of the power
is read page 0x13 address 0x1c bit 10 = 1, or manually, by writing a 0 (arming) and then a 1 (firing) to page 0x13
address 0x1c bit 11, (page 0x13 address 0x12 bit10 must be 0). There should be two system clocks between writing
the 0 and writing the 1, and two clocks after writing the 1, before rearming.
There are two status bits, too_soon bit13 and missed bit14. If the one shot is fired when the ready bit 15 is low, then
too_soon is set. The user must reset it. If done happens when the ready bit is set, the missed bit is set. Again, it is
reset by the user.
Example using a read of the msb to fire one shot:
1. Sync integration counter
2. Wait for ready bit to be 1 (8 clocks or less depending on sync source)
3. Read MSB of power (also fires one shot to clear ready bit) and ignore it.
4. Wait for ready bit to be 1
5. Read power LSB
6. Read power MSB
7. Check to be sure missed bit is not set
8. Go to step 4
NOTE: The too_soon bit is never set if ready is active when MSB is read.