Specifications

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SLWS142J − JANUARY 2003 − REVISED AUGUST 2007

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The step size can be set using four values of D. The user can specify separate values of D for when the magnitude

is:

below threshold (agc_Dblw),

above threshold (agc_Dabv),

consistently equal to zero (agc_Dzro),

or consistently equal to maximum (agc_Dsat).

This allows the user to set different attack and decay time constants.

The agc_Dzro and agc_Dsat can have shorter time constants for when the signal falls too low (nearly zero) or goes

too high (saturates).

The magnitude is considered to be consistently nearly zero by using a 4-bit counter that counts up every time the

8-bit magnitude value is nearly zero and counts down otherwise. Nearly zero is defined by and’ing the magnitude

with a zero mask before checking to see if it is zero. If the counter’s value exceeds a user specified threshold, then

agc_Dzro is used.

The magnitude is considered too high by counting the number of cycles where the count is greater than a maximum

magnitude. If the counter value exceeds a user specified threshold, then the agc_Dsat is used.

The AGC is also subject to user specified upper and lower adjustment limits. The AGC stops incrementing the gain

if the adjustment exceeds agc_max. It stops decrementing the gain if the adjustment is less than −agc_min. The

agc_max and agc_min bits are 16-bit values that line up with the most significant 16 bits of gain_msb and gain_lsb.

The input data is validated by a signal. For complex data, the I and Q samples are processed as if they were two

real samples. An adjustment is made for the magnitude of the I sample, and then another adjustment is made for

the Q sample.

The cmd5016 software will automatically program the agc circuit using the keywords overall_gain, agc_mode,

agc_tc, and agc_cf. See the GC5016 automatic gain control application note for details.

13.11 Fixed Gain Control

The AGC can be turned off by setting the agc_freeze control bit. The AGC adjustment loop is cleared using the

gain_sync control bit field. A static gain is set by setting G0 using the gain_lsb and gain_msb bit fields, by setting

agc_freeze, and by setting gain_sync to be always active. The gain_sync control can also be used to synchronize

gain changes across multiple channels or across multiple chips. The cmd5016 software will put the chip into the

fixedgain mode and will automatically calculate the correct values for gain_lsb and gain_msb based upon the

overall-gain keyword.

13.12 Receiver Output Interface (ROUTF)

This section describes the output interface of the GC5016 as a DDC. The receiver output has several different modes,

and different numbers of output pins and bit configurations. The receiver Output has several formats:

D Parallel IQ or real output − in this mode, there is one output per Frame Strobe and each channel is output on

its own pins.

D Interleaved IQ − in this mode, the Frame Strobe identifies the start of I of the interleaved IQ output. In this format,

I is output first, followed by Q Each channel is output on its own pins.

D Time Division Multiplexed IQ − in this mode, all of the DDC channels are output from the D output port, The Frame

Strobe identifies the start of each TDM frame. The output order in 4 channel mode is: ID, QD, IC, QC, IB, QB,

IA, QA. The output order in 2 channel split IQ mode is: QD, IC, QB, IA.

The output interface also allows AGC gain data to be output with the data.

The GC5016 has four 16-bit output ports. Each output port consists of 16 parallel output pins, a programmable divided

clock, and a frame strobe. The parallel output data pins for the GC5016 are AO[15..0], BO[15..0], CO[15..0], and

DO[15..0]. The letters A..D refer to the four separate channels A..D.