Specifications

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SLWS142J − JANUARY 2003 − REVISED AUGUST 2007

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Channel

Clk Sck_div = 1

ckp_N = 0

DDC

Output

Receive

Output

Sequence

Counter (int)

7 6 5 4 3 2 1 0

I(Q)

Channel

7 6 5

Channel

Clk Sck_div = 1

ckp_N = 1

Decimation = 16

BITS=16, PINS=16, OR BITS=8,PINS=8, OR BITS=4, PINS=4

DDC

Output

I(Q)MSB I(Q)LSB

BITS=20, PINS=16, OR BITS=16,12,PINS=8, OR BITS=8, PINS=4

DDC

Output

I(Q)MSB

BITS=20, PINS=8, OR BITS=12, PINS=4

DDC

Output

BITS=16, PINS=4

I(Q)MID I(Q)LSB

I(Q)MSB

I(Q)MID1 I(Q)MID2

I(Q)LSB

I(Q)

I(Q)MSB I(Q)LSB

I(Q)MSB

I(Q)MID I(Q)LSB

I(Q)MSB

I(Q)MID1 I(Q)MID2

h(o)

Figure 13. DDC Output Real or SplitIQ Timing Diagram