Specifications

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SLWS142J − JANUARY 2003 − REVISED AUGUST 2007
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29
CK
Channel
Clk Sck_div = 1
ckp_N = 0
DDC
Output
Receive
Output
Sequence
Counter (int)
7 6 5 4 3 2 1 0
I
Q
Channel
FS
7 6 5
Channel
Clk Sck_div = 1
ckp_N = 1
Decimation = 16
BITS=16, PINS=16, OR BITS=8,PINS=8, OR BITS=4, PINS=4
IQ
DDC
Output
IMSB ILSB
BITS=20, PINS=16, OR BITS=16,12,PINS=8, OR BITS=8, PINS=4
QMSB QLSB IMSB ILSB QMSB
DDC
Output
IMSB IMID
BITS=20, PINS=8, OR BITS=12, PINS=4
ILSB
QMSB
IMSB IMID ILSB
QMID QLSB
DDC
Output
IMSB IMID1
BITS=16, PINS=4
IMID2 ILSB IMSB IMID1 IMID2QMSB QMID1 QMID2 QLSB
t
h(o)
t
d
Figure 14. DDC Output Interleaved IQ Timing Diagram