Specifications

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SLWS142J − JANUARY 2003 − REVISED AUGUST 2007
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31
CK
Channel
Clk Sck_div = 1
ckp_N = 0
Receive
Output
Sequence
Counter (int)
7 6 5 4 3 2 1 0
Channel
FS
7 6 5
Channel
Clk Sck_div = 1
ckp_N = 1
Decimation = 16
DDC
Output
CH1I(A)
CH1Q(B)
SPLITIQ=1, BITS=16, PINS=16
DDC
Output
SPLITIQ=1 AND ((BITS=20, PINS=16) OR (BITS=16, PINS=8))
DDC
Output
SPLITIQ = 0, AND ( (BITS=16,PINS=16) OR (BITS=8, PINS=8))
CH2I(C)CH2Q(D)
CH2Q(D)MSB
CH2Q(C)MSB CH2Q(C )LSB
CH1Q(B)MSB CH1Q(B)LSB
CH1I(A)MSB CH1I(A)LSB
CH4I(D) CH4Q(D) CH3I(C) CH3Q(C) CH2I(B) CH2Q(B) CH1I(A) CH1Q(A)
CH2Q(D)LSB
CH1Q(B)CH2I(C)CH2Q(D)
CH2Q(D)MSB
CH2Q(C)MSB
CH4I(D) CH4Q(D) CH3I(C)
CH2Q(D)LSB
t
h(o)
t
d
Figure 15. DDC Output TDM Timing Diagram