Specifications

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SLWS142J − JANUARY 2003 − REVISED AUGUST 2007
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The double rate DUC mode utilizes the splitIQ mode with special CIC filter special mixer, and special output port
programming. The double rate mode has two output ports versus one, as there are even and odd DUC outputs. The
CIC filters produce even and odd sample outputs at the CK rate. The cmd5016 software keyword ’toutf_rate 2’
controls the double rate mode,
14.2 Transmit Input Interface
The Transmit Input Interface connects the customer input with the Gain Block. The Transmit Input has several
formats, and programming modes:
Real Data − The channel input is real data.
8bit parallel IQ Data − The channel input is complex. Each 16 bit port accepts 8 bits of I and 8 bits of Q.
Parallel IQ Data − Two input ports are used for a complex input. I is input on one port, Q on the other. This mode
limits the chip to only two input ports.
Interleaved IQ Data − One input port is used to transfer each complex input. Several channel clocks are needed to
transfer the IQ input data.
Time Division Multiplexed (TDM) IQ Data − The A input port is used to input the channel IQ input data for all four
channels. Several channels clocks are needed to transfer in the IQ data.
Several cmd5016 software keywords are used to specify the Transmit Input Delay and Transmit Input Formatter
modes. The cmd5016 keywords are:
D fir_int, cic_int − interpolation ratio
D fir_coef − the filter symmetry and number of coefficients
D sck_div −sets the Frame Strobe width and the input data clock rate (period in CK clocks)
D tinf_fs_dly − term used to adjust the delay between the Frame Strobe output and the first IQ data sample in the
frame
D splitiq, splitiq_AB, splitiq_CD − sets the split IQ mode
D tinf_cmplx − identifies the input data as complex
D tinf_tdm − identifies that all channels are Time Multiplexed on port A inputs
D tinf_pariq −identifies the 8bit parallel IQ input mode
D tinf_iqmux −identifies the interleaved IQ mode
MODE NAME splitiq tinf_cmplx tinf_tdm tinf_pariq
Real 1 0 0 0
8bit parallel IQ 0 1 0 1
Parallel IQ 1 0 0 0
Interleaved IQ 0 1 0 0
TDM IQ 0 1 1 0
TDM IQ(splitiQ) 1 0 1 0
TDM IQ(parIQ) 0 1 1 1
14.2.1 Frame Strobe
Each channel has its own Frame Strobe generator that outputs a Frame Strobe when it needs a new input sample.
The period between each Frame Strobe is determined by the interpolation ratio.
The divided clock determines the width of the Frame Strobe and data signals. The Frame Strobe, 1−>0 transition
is used to identify the start of the input frame. See Figures 17 through 19.
The DUC channel outputs the Frame Strobe when it needs a new sample. The user can program the delay in divided
clocks between the frame strobe output and when the first value for the frame is clocked into the chip. This delay
is set in the cmd5016 software using the tinf_fs_dly keyword.
14.2.2 Input Clocking
The incoming data is clocked by the rising edge of the GC5016 clock CK.