Specifications

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SLWS142J − JANUARY 2003 − REVISED AUGUST 2007
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The sck_div can be used to program the GC5016 receive data every second, third, etc., clock edge, allowing the data
source to supply data at a lower speed. The user controls the clock division using sck_div. A value of 0 means that
every clock edge is used; a value of 1 means that every other clock edge is used, etc. The clock division phasing
is controlled by a general sync (sck_sync).
The time (in CK clocks) between data frames is the product of PFIR interpolation (fir_int) and CIC interpolation
(cic_int). The divided clock must divide this evenly, so (cic_int x fir_int) modulo (sck_div+1) must be 0 for the framing
to be fixed length. Otherwise, the length varies between two values.
There need to be enough divided clocks per frame to receive the entire frame of data. This means that (cic_int x fir_int
)/(sck_div + 1) must be greater than or equal to (bits/pins) x (2 if complex) x (nchannels if TDM). The CMD5016
software checks these constraints.
The divided clock outputs [A..D]CK are used primarily in the GC5016’s DDC receive mode, but may be of use in some
transmit applications − either as a data bit to indicate when data should be valid or in low frequency applications as
a clock. They are generated by dividing the GC5016’s main clock CK by programmable dividers sck_div+1 for each
channel. The input data transfer clock rate is then CK/(sck_div+1). The clock dividers can be synchronized by the
methods described in the Synchronization section. The polarity of each divided port clock [A..D]CK is user
programmable. For many applications, the input data transfer clock rate is the same as the main clock CK. In this
case, the output [A−D]CK should be ignored.
The divided clocks [A..D]CK are clocked out of the chip on the rising edge CK . The input data is clocked into the
chip on the rising edge of CK just before the rising edge of the divided clock (see Figure 19).
14.2.3 Bits and Pins
The user can select the number of data bits input to the GC5016 per divided clock cycle. The bits keyword in the
cmd5016 software selects the total number of data bits per input word. The allowable values are 4,8,12, 16, and 20
bits. The pins keyword selects the number of input port pins to use. The allowable values for the pins are 4,8, or 16.
This means that there will be ”pins” bits transferred for every divided clock cycle.
Transmit Input Mode Bits Pins Port Pins Used Number of Divided Clocks for I and Q, or I
20 16 15..0 2
16,12 16 15..0 1
20 8 15..8 3
16,12 8 15..8 2
Real, or Parallel IQ
8 8 15..8 1
Real, or Parallel IQ
20 4 15..12 5
16 4 15..12 4
12 4 15..12 3
8 4 15..12 2
8bit I and Q 8 16 15..0 1
20 16 15..0 4
16,12 16 15..0 2
20 8 15..8 6
16,12 8 15..8 4
Interleaved IQ Data
8 8 15..8 2
Interleaved IQ Data
20 4 15..12 10
16 4 15..12 8
12 4 15..12 6
8 4 15..12 4