Specifications

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SLWS142J − JANUARY 2003 − REVISED AUGUST 2007

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37

ACK

Sck_Div=1

AFS

I(Q)

AIn[ ]

tinf_fs_dly = 1

Interpolation Ratio = 24

CK

ACK

Sck_Div=1

ck_pol = 1

(BITS=16, PINS=16) OR (BITS=8, PINS=8)

I(Q)MSB I(Q)LSB

AIn[ ]

(BITS=20, PINS=16) OR (BITS=12,16, PINS=8)

AIn[ ]

(BITS=20, PINS=8) OR ( BITS=12, PINS=4)

AIn[ ]

BITS=16, PINS=4

I(Q)MID

I(Q)MID1 I(Q)MID2

I(Q)MSB

I(Q)MSB

I(Q)LSB

I(Q)LSB

I(Q)

I(Q)MSB I(Q)LSB

I(Q)MID

I(Q)MID1 I(Q)MID2

I(Q)MSB

I(Q)MSB

I(Q)LSB

I(Q)LSB

Figure 17. DUC Real or SplitIQ Input Timing Diagram, sck_div = 1, tinf_fs_dly 1