Specifications

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SLWS142J − JANUARY 2003 − REVISED AUGUST 2007
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ACK
Sck_Div=1
AFS
AI AQ BI BQ CI CQn DIn DQn
AIn[ ]
tinf_fs_dly = 1
Interpolation Ratio = 24
CK
ACK
Sck_Div=1
ck_pol = 1
SPLITIQ = 0 AND ( (BITS=16, PINS=16) OR (BITS=8, PINS=8))
AI AQ BI BQ
AIn[ ]
SPLITIQ = 1 AND ( (BITS=16, PINS=16) OR (BITS=8, PINS=8))
AI(MSB) AI(LSB) AQ(MSB) BI(MSB) BI(LSB) BQ(MSB) BQ(LSB)
AIn[ ]
SPLITIQ = 1 AND ( (BITS=20, PINS=16) OR (BITS=16,12, PINS=8))
AQ(LSB)
AI AQ BI BQ AI AQ BI BQ
AI(MSB) AI(LSB) AQ(MSB) AQ(LSB)
Figure 18. DUC TDM Input Timing Diagram, sck_div = 1, tinf_fs_dly 1