Specifications

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SLWS142J − JANUARY 2003 − REVISED AUGUST 2007
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40
ACK
Sck_Div=1
AFS
IQ
AIn[ ]
tinf_fs_dly = 1
Interpolation Ratio = 24
CK
ACK
Sck_Div=1
ck_pol = 1
(BITS=16, PINS=16) OR (BITS=8, PINS=8)
IMSB ILSB QMSB QLSB
AIn[ ]
(BITS=20, PINS=16) OR (BITS=12,16, PINS=8)
AIn[ ]
(BITS=20, PINS=8) OR ( BITS=12, PINS=4)
AIn[ ]
BITS=16, PINS=4
QMSB QMID QLSBIMSB IMID1 ILSB
IMSB IMID1 IMID2 QMSB QMID1 QMID2ILSB QLSB
IQ
IMSB ILSB QMSB QLSB
QMSBIMSB IMID1 ILSB
IMSB IMID1 IMID2 ILSB
Figure 19. DUC IntIQ Input Timing Diagram, sck_div = 1, tinf_fs_dly 1