Specifications

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SLWS142J − JANUARY 2003 − REVISED AUGUST 2007
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CE
t
REC
RD
t
su(C)
t
CSPW
A [4:0]
WRITE CYCLE − NORMAL MODE
t
su(EWC)
C [15:0]
t
h(C)
WR
Figure 28. Dual Strobe Edge Mode Write Timing
16.3 Single Strobe, Edge Mode(WRMODE = 0), Control Bus Timing
(See Figures 29 and 30)
Some processors provide a single control RD/WR together with a chip strobe that controls timing. In this case, the
RD pin can be grounded. The control processor must set A[4..0] to the desired register address, set WR low for a
write or high for a read, and select the chip by setting CE low. The write cycle is active while both CE and WR are
low. Data on the C[15..0] is registered into the chip on the rising edge of CE.