Specifications

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SLWS142J − JANUARY 2003 − REVISED AUGUST 2007
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16.4 Dual Strobe, Latch Mode(WRMODE = 1), Control Bus Timing (See Figure 31)
Latch mode (WRMODE=1) is used if the data is stable over the entire time period the write strobe is active. The data
on C[15..0] is transferred to the control registers during the entire time both WR and CE are low. Since some control
registers (such as most sync registers) are sensitive to transient values on the C[0:15] data bus, the data must be
stable during the entire write pulse in this mode.
CE
RD
t
REC
t
CSPW
A [4:0]
t
su(C)
WRITE CYCLE − LATCH MODE
C
[15:0]
t
h(C)
WR
t
su(EWC)
Figure 31. Dual Strobe Latch Mode Write Timing